Fully Accurate 16-Bit V nanoDAC OUT SPI Interface 2.7 V to 5.5 V in an MSOP Data Sheet AD5063 FEATURES FUNCTIONAL BLOCK DIAGRAM V V REF DD Single 16-bit DAC, 1 LSB INL Power-on reset to midscale AD5063 POWER-ON Guaranteed monotonic by design BUF R FB RESET 3 power-down functions INV Low power serial interface with Schmitt-triggered inputs REF(+) DAC V 10-lead MSOP, low power OUT DAC REGISTER Fast settling time of 1 s maximum (AD5063-1 model) 2.7 V to 5.5 V power supply AGND Low glitch on power-up INPUT POWER-DOWN CONTROL RESISTOR Unbuffered voltage capable of driving 60 k load CONTROL LOGIC LOGIC NETWORK SYNC interrupt facility APPLICATIONS SYNC SCLK DIN DACGND Process control Figure 1. Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD5063, a member of the Analog Device Inc., nanoDAC family, is a low power, single 16-bit, unbuffered voltage-output 1. Available in 10-lead MSOP. DAC that operates from a single 2.7 V to 5 V supply. The device 2. 16-bit accurate, 1 LSB INL. offers a relative accuracy specification of 1 LSB, and operation 3. Low glitch on power-up. is guaranteed monotonic with a 1 LSB DNL specification. The 4. High speed serial interface with clock speeds up to 30 MHz. AD5063 comes with on-board resistors in a 10-lead MSOP, 5. Three power-down modes available to the user. allowing bipolar signals to be generated with an output amplifier. The device uses a versatile 3-wire serial interface that operates Table 1. Related Devices at clock rates up to 30 MHz and that is compatible with Part No. Description standard SPI, QSPI, MICROWIRE, and DSP interface AD5061 2.7 V to 5.5 V, 16-bit nanoDAC D/A, standards. The reference for the AD5063 is supplied from an 4 LSBs INL, SOT-23. external V pin. A reference buffer is also provided on-chip. REF AD5062 2.7 V to 5.5 V, 16-bit nanoDAC D/A, The device incorporates a power-on reset circuit that ensures 1 LSB INL, SOT-23. the DAC output powers up to midscale and remains there until AD5040/AD5060 2.7 V to 5.5 V, 14-/16-bit nanoDAC D/A, a valid write to the device takes place. The device contains a 1 LSB INL, SOT-23. power-down feature that reduces the current consumption of the device to typically 300 nA at 5 V and provides software- selectable output loads while in power-down mode. The device is put into power-down mode via the serial interface. Total unadjusted error for the device is <1 mV. This device exhibits very low glitch on power-up. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20052018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 04766-001AD5063 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 13 Applications ....................................................................................... 1 Input Shift Register .................................................................... 13 Functional Block Diagram .............................................................. 1 SYNC Interrupt .......................................................................... 13 General Description ......................................................................... 1 Power-On to Midscale ............................................................... 14 Product Highlights ........................................................................... 1 Software Reset ............................................................................. 14 Revision History ............................................................................... 2 Power-Down Modes .................................................................. 14 Specifications ..................................................................................... 3 Microprocessor Interfacing ....................................................... 14 Timing Characteristics ................................................................ 5 Applications Information .............................................................. 16 Absolute Maximum Ratings ............................................................ 6 Choosing a Reference for the AD5063 .................................... 16 ESD Caution .................................................................................. 6 Bipolar Operation Using the AD5063 ..................................... 16 Pin Configuration and Function Descriptions ............................. 7 Using the AD5063 with a Galvanically Isolated Interface Chip .............................................................................................. 17 Typical Performance Characteristics ............................................. 8 Power Supply Bypassing and Grounding ................................ 17 Terminology .................................................................................... 12 Outline Dimensions ....................................................................... 18 Theory of Operation ...................................................................... 13 Ordering Guide .......................................................................... 18 DAC Architecture ....................................................................... 13 Reference Buffer ......................................................................... 13 REVISION HISTORY Change to Serial Interface Section ............................................... 13 4/2018Rev. C to Rev. D Change to Table 6 ........................................................................... 14 Changed Application Section to Applications Information Change to Bipolar Operation Using the AD5063 Section ........ 16 Section .............................................................................................. 16 Changes to Bipolar Operation Using the AD5063 Section and 7/2005Rev. 0 to Rev. A Figure 37 .......................................................................................... 16 Changes to Galvanically Isolated Chip Section .......................... 17 Changes to Ordering Guide .......................................................... 18 Changes to Figure 38 ...................................................................... 17 8/2009Rev. B to Rev. C 4/2005Revision 0: Initial Version Changes to Features Section............................................................ 1 Changes to Output Voltage Settling Time Parameter, Table 2 ... 3 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18 3/2006Rev. A to Rev. B Updated Format .................................................................. Universal Change to Features ........................................................................... 1 Change to Figure 1 ........................................................................... 1 Changes to Specifications ................................................................ 3 Change to Absolute Maximum Ratings ......................................... 6 Change to Reference Buffer Section............................................. 13 Rev. D Page 2 of 18