Fully Accurate, 12-/14-/16-Bit V nanoDAC, Quad, OUT SPI Interface, 4.5 V to 5.5 V in TSSOP Data Sheet AD5024/AD5044/AD5064 FEATURES FUNCTIONAL BLOCK DIAGRAMS V V DD REFIN Low power quad 12-/14-/16-bit DAC, 1 LSB INL AD5064-1 Pin compatible and performance upgrade to AD5666 LDAC BUFFER INPUT DAC DAC A V A OUT Individual and common voltage reference pin options REGISTER REGISTER SCLK BUFFER DAC Rail-to-rail operation INPUT V B DAC B OUT REGISTER REGISTER INTERFACE SYNC LOGIC AND 4.5 V to 5.5 V power supply SHIFT BUFFER INPUT DAC REGISTER DAC C VOUTC REGISTER REGISTER DIN Power-on reset to zero scale or midscale BUFFER INPUT DAC DAC D V D OUT REGISTER REGISTER 3 power-down functions and per-channel power-down SDO POWER-ON POWER-DOWN RESET LOGIC Hardware LDAC with software LDAC override function POR GND CLR function to programmable code LDAC CLR Figure 1. AD5064-1 Functional Equivalent and Pin Compatible with AD5666 SDO daisy-chaining option V V A V B 14-/16-lead TSSOP DD REF REF AD5024/ Internal reference buffer and internal output amplifier AD5044/ AD5064 LDAC BUFFER INPUT DAC V A DAC A OUT REGISTER REGISTER APPLICATIONS SCLK BUFFER INPUT DAC DAC B V B INTERFACE OUT REGISTER REGISTER Process control LOGIC AND SYNC SHIFT BUFFER REGISTER DAC INPUT V C Data acquisition systems DAC C OUT REGISTER REGISTER DIN BUFFER Portable battery-powered instruments INPUT DAC DAC D V D OUT REGISTER REGISTER Digital gain and offset adjustment POWER-ON POWER-DOWN RESET LOGIC Programmable voltage and current sources POR V C V D GND LDAC CLR REF REF Programmable attenuators Figure 2. AD5024/AD5044/AD5064 with Individual Reference Pins GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD5024/AD5044/AD5064/AD5064-1 are low power, quad 1. Quad channel available in 14-/16-lead TSSOPs. 12-/14-/16-bit buffered voltage output nanoDAC converters 2. 16-bit accurate, 1 LSB INL. that offer relative accuracy specifications of 1 LSB INL and 1 LSB 3. High speed serial interface with clock speeds up to 50 MHz. DNL with the AD5024/AD5044/AD5064 individual reference 4. Reset to known output voltage (zero scale or midscale). pin and the AD5064-1 common reference pin options. The Table 1. Related Devices AD5024/AD5044/AD5064/AD5064-1 can operate from a single Device No. Description 4.5 V to 5.5 V supply. The AD5024/AD5044/AD5064/AD5064-1 AD5666 Quad,16-bit buffered DAC, also offer a differential accuracy specification of 1 LSB. The 16 LSB INL, TSSOP devices use a versatile 3-wire, low power Schmitt trigger serial AD5025/AD5045/AD5065 Dual, 16-bit buffered DACs, interface that operates at clock rates up to 50 MHz and is compati- 1 LSB INL, TSSOP ble with standard SPI, QSPI, MICROWIRE, and DSP interface AD5062, AD5063 16-bit nanoDAC, 1 LSB INL, SOT-23, standards. Integrated reference buffers and output amplifiers are MSOP also provided on-chip. The AD5024/AD5044/AD5064/AD5064-1 AD5061 16-bit nanoDAC, 4 LSB INL, SOT-23 incorporate a power-on reset circuit that ensures the DAC AD5040/AD5060 14-/16-bit nanoDAC, 1 LSB INL, output powers up to zero scale or midscale and remains there SOT-23 until a valid write takes place to the device. The AD5024/AD5044/ AD5064/AD5064-1 contain a power-down feature that reduces the current consumption of the device to typically 400 nA at 5 V and provides software selectable output loads while in power- down mode. Total unadjusted error for the devices is <2 mV. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 06803-001 06803-064AD5024/AD5044/AD5064 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Amplifier ........................................................................ 19 Applications ....................................................................................... 1 Serial Interface ............................................................................ 19 Functional Block Diagrams ............................................................. 1 Shift Register ............................................................................... 19 General Description ......................................................................... 1 Modes of Operation ................................................................... 21 Product Highlights ........................................................................... 1 Power-On Reset .......................................................................... 22 Revision History ............................................................................... 2 Power-Down Modes .................................................................. 22 Specif icat ions ..................................................................................... 3 Clear Code Register ................................................................... 23 AC Characteristics ........................................................................ 4 LDAC Function .......................................................................... 23 Timing Characteristics ................................................................ 5 Power Supply Bypassing and Grounding ................................ 24 Absolute Maximum Ratings ............................................................ 7 Microprocessor Interfacing ....................................................... 25 ESD Caution .................................................................................. 7 Applications Information .............................................................. 26 Pin Configurations and Function Descriptions ........................... 8 Using a Reference as a Power Supply ....................................... 26 Typical Performance Characteristics ........................................... 10 Bipolar Operation....................................................................... 26 Terminology .................................................................................... 17 Using the AD5024/AD5044/AD5064/AD5064-1 with a Galvanically Isolated Interface ................................................. 26 Theory of Operation ...................................................................... 19 Outline Dimensions ....................................................................... 27 Digital-to-Analog Converter .................................................... 19 Ordering Guide .......................................................................... 28 DAC Architecture ....................................................................... 19 Reference Buffer ......................................................................... 19 REVISION HISTORY 6/2016Rev. F to Rev. G Changes to Timing Characteristics Section and Table 4 .............. 5 Changed ADSP-BF53x to ADSP-BF527 ..................... Throughout Added Circuit and Timing Diagrams Section and Figure 3 ........ 5 Changes to Power-On Reset Section ............................................ 22 Added Figure 5 ................................................................................... 6 Changes to Figure 4 ........................................................................... 6 Added Figure 6 ................................................................................... 8 6/2013Rev. E to Rev. F Change to Standalone Mode Section ........................................... 21 Added Table 6 Renumbered Sequentially ..................................... 8 Changed Input Shift Register to Shift Register Throughout ....... 8 5/2011Rev. D to Rev. E Changes to Table 7 ............................................................................. 9 Changes to Table 4 ............................................................................ 5 Changes to Typical Performance Characteristics Section ........ 10 Changes to Figure 4 and Figure 5 ................................................... 6 Changes to Terminology Section ................................................. 17 Changes to Digital-to-Analog Converter Section, Reference 8/20Rev. C to Rev. D Buffer Section, Output Amplifier Section, Serial Interface Change to Minimum SYNC High Time (Single Channel Section, Shift Register Section, and Table 8 ................................ 19 Changes to Figure 47, Figure 48, and Figure 49 Captions ........ 20 Update) Parameter, Table 4 ............................................................. 5 Added Modes of Operation Section, Daisy-Chaining Section, Table 10, and Table 11 .................................................................... 21 5/2010Rev. B to Rev. C Changes to Table 13 and Power-Down Mode Section .............. 22 Changes to Power-On Reset Section ............................................ 22 Changes to Table 16 ....................................................................... 24 Changes to Figure 52 to Figure 55 ................................................ 25 6/2009Rev. A to Rev. B Changes to Bipolar Operation Section and Figure 56 to Changes to Figure 1 .......................................................................... 1 Figure 58 .......................................................................................... 26 Added Figure 59 ............................................................................. 27 3/2009Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 27 Added 14-Lead TSSOP ...................................................... Universal Changes to Ordering Guide .......................................................... 28 Added Figure 1 Renumbered Sequentially .................................. 1 Changes to Features Section, General Description Section, 8/2008Revision 0: Initial Version Product Highlights Section, Figure 2, and Table 1 ....................... 1 Changes to Table 2 ............................................................................ 3 Rev. G Page 2 of 28