System Ready, 18-Bit 1 LSB INL, Voltage Output DAC Data Sheet AD5780 FEATURES FUNCTIONAL BLOCK DIAGRAM V V V CC DD REFP True 18-bit voltage output DAC, 1 LSB INL 8 nV/Hz output noise spectral density R R1 FB 6.8k 6.8k AD5780 0.025 LSB long-term linearity error stability A1 IOV R CC FB 0.018 ppm/C gain error temperature coefficient INV SDIN INPUT 2.5 s output voltage settling time 18 18 SHIFT 18-BIT DAC SCLK V OUT REGISTER DAC REG 3.5 nV-sec midscale glitch impulse AND SYNC CONTROL Integrated precision reference buffers LOGIC SDO Operating temperature range: 40C to +125C 6k LDAC 4 mm 5 mm LFCSP package CLR POWER-ON RESET Wide power supply range of up to 16.5 V AND CLEAR LOGIC RESET 35 MHz Schmitt triggered digital interface 1.8 V-compatible digital interface DGND V AGND V SS REFN Figure 1. APPLICATIONS Medical instrumentation Test and measurement Industrial control Scientific and aerospace instrumentation Data acquisition systems Digital gain and offset adjustment Power supply control GENERAL DESCRIPTION 1 The AD5780 is a true 18-bit, unbuffered voltage output digital- PRODUCT HIGHLIGHTS to-analog converter (DAC) that operates from a bipolar supply 1. True 18-bit accuracy. of up to 33 V. The AD5780 accepts a positive reference input 2. Wide power supply range of up to 16.5 V. range of 5 V to VDD 2.5 V and a negative reference input range 3. 40C to +125C operating temperature range. of V + 2.5 V to 0 V. Both reference inputs are buffered on chip SS 4. Low 8 nV/Hz noise. and external buffers are not required. The AD5780 offers a 5. Low 0.018 ppm/C gain error temperature coefficient. relative accuracy specification of 1 LSB maximum range, and COMPANION PRODUCTS operation is guaranteed monotonic with a 1 LSB differential nonlinearity (DNL) maximum range specification. Output Amplifier Buffer: AD8675, ADA4898-1, ADA4004-1 The part uses a versatile 3-wire serial interface that operates at External Reference: ADR445, ADR4550 clock rates of up to 35 MHz and is compatible with standard DC-to-DC Design Tool: ADIsimPower serial peripheral interface (SPI), QSPI, MICROWIRE, and Additional companion products on the AD5780 product page. DSP interface standards. The part incorporates a power-on reset circuit that ensures that the DAC output powers up to 0 V Table 1. Related Devices in a known output impedance state and remains in this state Part No. Description until a valid write to the device takes place. The part provides AD5790 20-bit, 2 LSB accurate DAC an output clamp feature that places the output in a defined load AD5791 20-bit, 1 ppm accurate DAC state. AD5781 18-bit, 0.5 LSB accurate DAC AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC AD5760 16-bit, 0.5 LSB accurate DAC 1 Protected by U.S. Patent No. 7,884,747 and 8,089,380. Rev. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 09649-001AD5780 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DAC Architecture ....................................................................... 18 Applications ....................................................................................... 1 Serial Interface ............................................................................ 18 Functional Block Diagram .............................................................. 1 Hardware Control Pins .............................................................. 19 General Description ......................................................................... 1 On-Chip Registers ...................................................................... 19 Product Highlights ........................................................................... 1 AD5780 Features ............................................................................ 23 Companion Products ....................................................................... 1 Power-On to 0 V ......................................................................... 23 Revision History ............................................................................... 2 Power-Up Sequence ................................................................... 23 Specifications ..................................................................................... 3 Configuring the AD5780 .......................................................... 23 Timing Characteristics ................................................................ 5 DAC Output State ...................................................................... 23 Absolute Maximum Ratings ............................................................ 7 Output Amplifier Configuration.............................................. 23 ESD Caution .................................................................................. 7 Applications Information .............................................................. 25 Pin Configuration and Function Descriptions ............................. 8 Typical Operating Circuit ......................................................... 25 Typical Performance Characteristics ............................................. 9 Evaluation Board ........................................................................ 26 Terminology .................................................................................... 17 Outline Dimensions ....................................................................... 27 Theory of Operation ...................................................................... 18 Ordering Guide .......................................................................... 27 REVISION HISTORY 3/2012Rev. B to Rev. C 4/2018Rev. E to Rev. F Changes to Data Sheet Title and added Patent 8,089,380 ............ 1 Added Power-Up Sequence Section and Figure 50 Renumbered Sequentially ..................................................................................... 23 2/2012Rev. A to Rev. B Updated Outline Dimensions ....................................................... 27 Deleted Linearity Compensation Section ................................... 24 Changes to Ordering Guide .......................................................... 27 12/2011Rev. 0 to Rev. A 7/2013Rev. D to Rev. E Edits to Table 2 ...................................................................................3 Changes to t Test Conditions/Comments and Endnote 2 ......... 5 1 Changes to Figure 48 ...................................................................... 17 Deleted Figure 4 ................................................................................ 7 Changes to DAC Register Section ................................................ 21 Changes to Pin 11 Description ....................................................... 8 Changes to Table 10 and Table 11 ................................................ 22 Deleted Daisy-Chain Operation Section ..................................... 19 11/2011Revision 0: Initial Version 7/2012Rev. C to Rev. D Changes to Figure 53 ...................................................................... 24 Changes to Figure 55 ...................................................................... 26 Rev. F Page 2 of 27