16-Bit, 1.5 LSB INL, 500 kSPS PulSAR Differential ADC in MSOP/LFCSP Data Sheet AD7688 FEATURES APPLICATION DIAGRAM 0.5V TO 5V 5V 16-bit resolution with no missing codes Throughput: 500 kSPS INL: 0.4 LSB typ, 1.5 LSB max (23 ppm of FSR) VREF VIO 1.8V TO VDD Dynamic range: 96.5 dB REF VDD 0 SDI IN+ SNR: 95.5 dB at 20 kHz SCK AD7688 3- OR 4-WIRE INTERFACE IN THD: 118 dB at 20 kHz (SPI, DAISY CHAIN, CS) SDO VREF GND CNV True differential analog input range 0 V REF 0 V to V with V up to VDD on both inputs REF REF No pipeline delay Figure 2. Single-supply 5 V operation with Table 1. MSOP, LFCSP/SOT-23 16-Bit PulSAR ADC 1.8 V/2.5 V/3 V/5 V logic interface Type 100 kSPS 250 kSPS 500 kSPS Proprietary serial interface 1 True Differential AD7684 AD7687 AD7688 SPI/QSPI/MICROWIRE/DSP-compatible Pseudo AD7683 AD7685 AD7686 Daisy-chain multiple ADCs and BUSY indicator Differential/Unipolar AD7694 Power dissipation Unipolar AD7680 3.75 mW at 5 V/100 kSPS 3.75 W at 5 V/100 SPS Standby current: 1 nA GENERAL DESCRIPTION 10-lead MSOP (MSOP-8 size) and The AD7688 is a 16-bit, charge redistribution, successive 3 mm 3 mm LFCSP (SOT-23 size) approximation, analog-to-digital converter (ADC) that operates Pin-for-pin compatible with AD7685, AD7686, and AD7687 from a single 5 V power supply, VDD. It contains a low power, APPLICATIONS high speed, 16-bit sampling ADC with no missing codes, an Battery-powered equipment internal conversion clock, and a versatile serial interface port. Data acquisitions The part also contains a low noise, wide bandwidth, short Instrumentation aperture delay track-and-hold circuit. On the CNV rising edge, Medical instruments it samples the voltage difference between IN+ and IN pins. Process controls The voltages on these pins usually swing in opposite phase between 0 V and REF. The reference voltage, REF, is applied 1.5 POSITIVE INL = +0.31LSB externally and can be set up to the supply voltage. NEGATIVE INL = 0.39LSB 1.0 Its power scales linearly with throughput. The SPI-compatible serial interface also features the ability, 0.5 using the SDI input, to daisy-chain several ADCs on a single, 3-wire bus and provides an optional BUSY indicator. It is 0 compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply VIO. 0.5 The AD7688 is housed in a 10-lead MSOP or a 10-lead LFCSP with operation specified from 40C to +85C. 1.0 1.5 0 16384 32768 49152 65535 CODE 1 Protected by U.S. Patent 6,703,961. Figure 1. Integral Nonlinearity vs. Code Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20052014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. INL (LSB) 02973-001 02973-002AD7688 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 15 Applications ....................................................................................... 1 Single-to-Differential Driver .................................................... 15 Application Diagram ........................................................................ 1 Voltage Reference Input ............................................................ 15 General Description ......................................................................... 1 Power Supply ............................................................................... 15 Revision History ............................................................................... 2 Supplying the ADC from the Reference .................................. 16 Specif icat ions ..................................................................................... 3 Digital Interface .......................................................................... 16 Timing Specifications ....................................................................... 5 CS MODE 3-Wire, No BUSY Indicator .................................. 17 Absolute Maximum Ratings ............................................................ 6 CS Mode 3-Wire with BUSY Indicator ................................... 18 Thermal Resistance ...................................................................... 6 CS Mode 4-Wire, No BUSY Indicator ..................................... 19 ESD Caution .................................................................................. 6 CS Mode 4-Wire with BUSY Indicator ................................... 20 Pin Configuration and Function Descriptions ............................. 7 Chain Mode, No BUSY Indicator ............................................ 21 Terminology ...................................................................................... 8 Chain Mode with BUSY Indicator ........................................... 22 Typical Performance Characteristics ............................................. 9 Application Hints ........................................................................... 23 Circuit Information .................................................................... 12 Layout .......................................................................................... 23 Converter Operation .................................................................. 12 Evaluating the AD7688 Performance ...................................... 23 Typical Connection Diagram ................................................... 13 Outline Dimensions ....................................................................... 24 Analog Input ............................................................................... 14 Ordering Guide .......................................................................... 25 REVISION HISTORY 6/14Rev. A to Rev. B Added Patent Footnote .................................................................... 1 Change to Evaluating the AD7688 Performance Section ......... 23 Updated Outline Dimensions (Dimensions Not Changed, Lead-to-Pad Dimension Updated for JEDEC Compliance) ..... 24 Changes to Ordering Guide .......................................................... 25 2/11Rev. 0 to Rev. A Deleted QFN in Development Note ............................ Throughout Changes to Table 5 ............................................................................ 6 Added Thermal Resistance Section and Table 6 .......................... 6 Changes to Figure 6 and Table 7 ..................................................... 7 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 25 4/05Revision 0: Initial Version Rev. B Page 2 of 28