EVAL-ADCMP572BCPZ Analog Devices

Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators Data Sheet ADCMP572/ADCMP573 FEATURES FUNCTIONAL BLOCK DIAGRAM V V CCI CCO 3.3 V/5.2 V single-supply operation 150 ps propagation delay 15 ps overdrive and slew rate dispersion V TERMINATION TP 8 GHz equivalent input rise time bandwidth V NONINVERTING P 80 ps minimum pulse width Q OUTPUT INPUT ADCMP572 CML/ 35 ps typical output rise/fall ADCMP573 RSPECL V INVERTING N Q OUTPUT 10 ps deterministic jitter (DJ) INPUT 200 fs random jitter (RJ) V TERMINATION TN On-chip terminations at both input pins Robust inputs with no output phase reversal LE INPUT Resistor-programmable hysteresis HYS LE INPUT Differential latch control Figure 1. Extended industrial 40C to +125C temperature range APPLICATIONS Clock and data signal restoration and level shifting Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry GENERAL DESCRIPTION The ADCMP572 and ADCMP573 are ultrafast comparators provided at both inputs with the optional capability to be left fabricated on Analog Devices, Inc., proprietary XFCB3 Silicon open (on an individual pin basis) for applications requiring Germanium (SiGe) bipolar process. The ADCMP572 features high impedance inputs. CML output drivers and latch inputs, and the ADCMP573 The CML output stage is designed to directly drive 400 mV into features reduced swing PECL (RSPECL) output drivers and 50 transmission lines terminated to between 3.3 V to 5.2 V. latch inputs. The RSPECL output stage is designed to drive 400 mV into 50 Both devices offer 150 ps propagation delay and 80 ps terminated to V 2 V and is compatible with several commonly CCO minimum pulse width for 10 Gbps operation with 200 fs rms used PECL logic families. The comparator input stage offers robust random jitter (RJ). Overdrive and slew rate dispersion are protection against large input overdrive, and the outputs do not typically less than 15 ps. phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also A flexible power supply scheme allows both devices to operate provided. with a single 3.3 V positive supply and a 0.2 V to +1.2 V input signal range or with split input/output supplies to support a The ADCMP572 and ADCMP573 are available in a 16-lead wider 0.2 V to +3.2 V input signal range and an independent LFCSP package and have been characterized over an extended range of output levels. 50 on-chip termination resistors are industrial temperature range of 40C to +125C. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20052015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 04409-025ADCMP572/ADCMP573 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power/Ground Layout and Bypassing ........................................9 Applications ....................................................................................... 1 CML/RSPECL Output Stage ........................................................9 Functional Block Diagram .............................................................. 1 Using/Disabling the Latch Feature ..............................................9 General Description ......................................................................... 1 Optimizing High Speed Performance ..................................... 10 Revision History ............................................................................... 2 Comparator Propagation Delay Dispersion ........................... 10 Electrical Characteristics ................................................................. 3 Comparator Hysteresis .............................................................. 11 Absolute Maximum Ratings ............................................................ 5 Minimum Input Slew Rate Requirements .............................. 11 Thermal Considerations .............................................................. 5 Typical Application Circuits ......................................................... 12 ESD Caution .................................................................................. 5 Timing Information ....................................................................... 13 Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 14 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 14 Applications Information ................................................................ 9 REVISION HISTORY 3/15Rev. A to Rev. B Changes to Figure 2 and Table 3 ..................................................... 6 Changes to Figure 23 ...................................................................... 12 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 4/09Rev. 0 to Rev. A Changes to Figure 26 ...................................................................... 12 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 4/05Revision 0: Initial Version Rev. B Page 2 of 14