5 kV RMS/3.75 kV RMS, 600 Mbps, Dual-Channel LVDS Isolators Data Sheet ADN4650/ADN4651/ADN4652 FEATURES FUNCTIONAL BLOCK DIAGRAMS V V IN1 IN2 5 kV rms/3.75 kV rms LVDS isolator ADN4650 Complies with TIA/EIA-644-A LVDS standard ISOLATION LDO LDO BARRIER Multiple dual-channel configurations V V DD1 DD2 Up to 600 Mbps switching with low jitter D D IN1+ OUT1+ 4.5 ns maximum propagation delay D D IN1 OUT1 151 ps maximum peak-to-peak total jitter at 600 Mbps LVDS DIGITAL ISOLATOR LVDS 100 ps maximum pulse skew D D IN2+ OUT2+ 600 ps maximum part to part skew D IN2 D OUT2 2.5 V or 3.3 V supplies GND GND 75 dBc power supply ripple rejection and glitch immunity 1 2 8 kV IEC 61000-4-2 ESD protection across isolation barrier Figure 1. High common-mode transient immunity: >25 kV/s V V IN1 IN2 Passes EN55022 Class B radiated emissions limits with ADN4651 ISOLATION LDO LDO 600 Mbps PRBS BARRIER V V DD1 DD2 Safety and regulatory approvals (20-lead SOIC package) UL: 5000 V rms for 1 minute per UL 1577 D D IN1+ OUT1+ CSA Component Acceptance Notice 5A D D IN1 OUT1 LVDS DIGITAL ISOLATOR LVDS VDE certificate of conformity D D OUT2+ IN2+ DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 D D OUT2 IN2 VIORM = 424 V peak Fail-safe output high for open, short, and terminated input GND GND 1 2 conditions (ADN4651/ADN4652) Figure 2. Operating temperature range: 40C to +125C V V IN1 IN2 Choice of package and isolation options ADN4652 3.75 kV rms in highly integrated 20-lead SSOP ISOLATION LDO LDO BARRIER 5 kV rms in 20-lead SOIC with 7.8 mm creepage/clearance V V DD1 DD2 D D APPLICATIONS OUT1+ IN1+ D D OUT1 IN1 Analog front-end (AFE) isolation LVDS DIGITAL ISOLATOR LVDS Data plane isolation D D OUT2+ IN2+ Isolated high speed clock and data links D D OUT2 IN2 Isolated serial peripheral interface (SPI) over LVDS GND GND 1 2 GENERAL DESCRIPTION Figure 3. 1 The ADN4650/ADN4651/ADN4652 are signal isolated, low ensure a Logic 1 on the corresponding LVDS driver output voltage differential signaling (LVDS) buffers that operate at up when the inputs are floating, shorted, or terminated, but not to 600 Mbps with very low jitter. driven. The devices integrate Analog Devices, Inc., iCoupler technology, For high speed operation with low jitter, the LVDS and isolator enhanced for high speed operation, to provide galvanic isolation of circuits rely on a 2.5 V supply. An integrated on-chip low dropout the TIA/EIA-644-A compliant LVDS drivers and receivers. regulator (LDO) can provide the required 2.5 V from an external This technology allows drop-in isolation of an LVDS signal 3.3 V power supply. The devices are fully specified over a wide chain. industrial temperature range and are available in a 20-lead, Multiple channel configurations are offered, and the LVDS receivers wide body SOIC package with 5 kV rms isolation or a 20-lead on the ADN4651/ADN4652 include a fail-safe mechanism to SSOP package with 3.75 kV rms isolation. 1 Protected by U.S. Patents 5,952,849 6,873,065 6,903,578 and 7,075,329. Other patents are pending. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 13 67 7-10 3 13 677-10 1 13677-00 1ADN4650/ADN4651/ADN4652 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .......................................................................8 Applications ....................................................................................... 1 ESD Caution...................................................................................8 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ............................9 Functional Block Diagrams ............................................................. 1 Typical Performance Characteristics ........................................... 12 Revision History ............................................................................... 2 Test Circuits and Switching Characteristics ................................ 17 Specif icat ions ..................................................................................... 3 Theory of Operation ...................................................................... 18 Receiver Input Threshold Test Voltages .................................... 4 Truth Table and Fail-Safe Receiver .......................................... 18 Timing Specifications .................................................................. 4 Isolation ....................................................................................... 19 Insulation and Safety Related Specifications ............................ 5 PCB Layout ................................................................................. 19 Package Characteristics ............................................................... 6 Magnetic Field Immunity .......................................................... 19 Regulatory Information ............................................................... 6 Insulation Lifetime ..................................................................... 20 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Applications Information .............................................................. 22 Characteristics .............................................................................. 6 Outline Dimensions ....................................................................... 24 Recommended Operating Conditions ...................................... 7 Ordering Guide .......................................................................... 24 Absolute Maximum Ratings ............................................................ 8 REVISION HISTORY 6/2019Rev. D to Rev. E Changes to Skew Parameter and Fail-Safe Delay Parameter, Changes to Features Section............................................................ 1 Table 3 ................................................................................................. 4 Changed UL (Pending) Column to UL Column, CSA (Pending) Changes to Table 12 .......................................................................... 9 Column to CSA Column, VDE (Pending) Column to VDE Moved Figure 7 ............................................................................... 10 Column, Table 7, and DIN V VDE V 0884-10 (VDE V 0884-110) Added Table 13 ............................................................................... 10 Insulation Characteristics (Pending) Section to DIN V VDE V Added Figure 8 and Table 14, Renumbered Sequentially ......... 11 0884-10 (VDE V 0884-110) Insulation Characteristics Section ...... 6 Changes to PCB Layout Section ................................................... 19 Changes to Ordering Guide .......................................................... 24 1/2017Rev. C to Rev. D Changes to Ordering Guide .......................................................... 24 2/2016Rev. 0 to Rev. A Added ADN4650 ................................................................ Universal 9/2016Rev. B to Rev. C Changes to Features Section and General Description Section ........ 1 Added 20-Lead SSOP .................................................... Throughout Added Figure 1 Renumbered Sequentially ................................... 1 Changes to Title, Features Section, and General Description .... 1 Changes to Supply Current Parameter, Table 1 ............................. 3 Added Table 5 Renumbered Sequentially .................................... 5 Changes to Skew Parameter and Fail-Safe Delay Parameter, Change to Figure 5 ........................................................................... 7 Table 3 ................................................................................................. 4 Changes to PCB Layout Section ................................................... 19 Added Figure 5 ................................................................................... 9 Changes to Surface Tracking Section ........................................... 20 Changes to Table 12 .......................................................................... 9 Updated Outline Dimensions ....................................................... 24 Changes to Figure 30 Caption and Figure 31 Caption .............. 14 Changes to Ordering Guide .......................................................... 24 Change to Figure 34 ....................................................................... 15 Changes to Truth Table and Fail-Safe Receiver Section ............ 16 4/2016Rev. A to Rev. B Added Table 13 Renumbered Sequentially ................................ 16 Added ADN4652 ................................................................ Universal Change to Applications Information Section ............................. 20 Changes to Features Section and General Description Section ....... 1 Added Figure 41 ............................................................................. 20 Added Figure 3 Renumbered Sequentially .................................. 1 Changes to Ordering Guide .......................................................... 22 Changes to Supply Current Parameter, Table 1 ............................ 3 11/2015Revision 0: Initial Version Rev. E Page 2 of 25