Circuit Note CN-0256 Devices Connected/Referenced ADN4663 Dual Channel LVDS Driver Circuits from the Lab reference circuits are engineered and tested for quick and easy system integration to help solve todays ADN4664 Dual Channel LVDS Receiver analog, mixed-signal, and RF design challenges. For more ADuM3442 Quad Channel Digital Isolator information and/or support, visit www.analog.com/CN0256. ADuM5000 Isolated DC-to-DC Converter Isolated LVDS Interface Circuit LVDS links in industrial and instrumentation applications are EVALUATION AND DESIGN SUPPORT met that include the following: Circuit Evaluation Boards Isolation of the logic signals to/from the LVDS drivers/ CN-0256 Circuit Evaluation Board (EVAL-CN0256-EBZ) receivers, ensuring standard LVDS communication on the Design and Integration Files bus side of the circuit. Schematics, Layout Files, Bill of Materials Highly integrated isolation using just two additional wide- CIRCUIT FUNCTION AND BENEFITS body SOIC devices, the ADuM3442 and ADuM5000, to Low voltage differential signaling (LVDS) is an established isolate the standard LVDS devices, the ADN4663 and standard (TIA/EIA-644) for low power, high speed, point-to- ADN4664. point communication. It is used in instrumentation and control Low power consumption compared to traditional isolation applications to send high volumes of data across backplanes or (opto-couplers). Low power operation is a feature of LVDS short cable links, or to distribute high speed clocks to different applications. parts of an application circuit. Multiple channels of isolation. In LVDS applications, The circuit shown in Figure 1 demonstrates isolation of an LVDS parallel channels are used to maximize data throughput. interface. Advantages of isolating LVDS interfaces include This circuit demonstrates quad-channel isolation (in this protection against fault conditions (safety isolation) and case, two transmit and two receive channels). improving robustness (functional isolation). High speed operation the isolation can operate at up to 150 Mbps, facilitating basic LVDS speed requirements. The ADuM3442 provides digital isolation of the logic inputs to the ADN4663 LVDS driver and the logic outputs from the The circuit shown in Figure 1 isolates a dual-channel LVDS ADN4664 LVDS receiver. Together with provision of isolated line driver and a dual-channel LVDS receiver. This allows power using the ADuM5000, a number of challenges to isolating demonstration of two complete transmit and receive paths on a single board. ADuM5000 GND 3.3V ISO 3.3V V CC OSC REC V ISO 3.3V DD1 ADN4663 D OUT1+ REG D IN1 V ISO D OUT1 V V DD1 DD2 D IN2 D OUT2+ ADuM3442 ISO 3.3V IN1 D OUT2 V CC LVDS BUS IN2 ADN4664 R IN1+ R OUT1 R1 100 OUT1 R IN1 R OUT2 OUT2 R IN2+ R2 100 R IN2 FPGA ISOLATION BARRIER Figure 1. Isolated LVDS Interface Circuit (Simplified Schematic, All Connections Not Shown) Rev. 0 Circuits from the Lab circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices Tel: 781.329.4700 www.analog.com be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) Fax: 781.461.3113 2012 Analog Devices, Inc. All rights reserved. 10386-001CN-0256 Circuit Note Guidelines described in the AN-0971 Application Note, CIRCUIT DESCRIPTION Recommendations for Control of Radiated Emissions with isoPower Applications of isolated LVDS are safety isolation and/or Devices, were used to generate the circuit layout. Additionally, functional isolation of board-to-board, backplane, and printed the layout has been optimized for high speed differential signaling. circuit board (PCB) communication links. An example of safety The LVDS input/output traces are of matched length and have isolation is a system with an LVDS backplane where one or more 50 impedance to ground (100 between differential pairs). plug-in cards are at risk from high voltage transients. Isolating Test points on each pair are also a matched distance from the the LVDS interface ensures that such fault conditions do not driver/receiver. Multiple vias to ground are placed alongside affect other circuits in the system. An example of an application the traces to improve signal integrity at high speeds. where functional isolation is beneficial is measurement equipment. Termination resistors (R1, R2) of 100 are fitted on the LVDS Isolating LVDS links, for example, between an ADC and FPGA, inputs RIN1+, RIN1 and RIN2+, RIN2. Terminate the can provide a floating ground plane to boost the integrity of measurement data, minimizing interference from the rest of receiving end of any bus connected to DOUT1+, DOUT1 the application. and DOUT2+, DOUT1. Figure 2 shows a photo of the isolated LVDS interface circuit Power and ground are connected via a screw-wire connector shown isolating two transmit communication channels (VDD1 and GND1). Logic inputs (IN1, IN2)/outputs (OUT1, OUT2) are connected via four SMB connectors. The bus signals (CMOS/TTL to LVDS) and two receive channels (LVDS to are similarly connected via eight SMB connectors. These connect to CMOS/TTL). The signals can be isolated at data rates up to the LVDS driver (ADN4663) and receiver (ADN4664) on traces 150 Mbps while maintaining the ADuM3442 specification for maximum pulse width distortion. with impedances of 50 to ground. CIRCUIT EVALUATION AND TEST To power the isolated LVDS interface circuit board, apply a 3.3 V or 5 V supply to VDD1. To test that the circuit is powered correctly, check the voltage level at the VDD2 test point. This test point is the isolated supply from the ADuM5000 and should be 3.3 V or 5 V nominally. A complete transmit and receive path can be tested by connecting the LVDS outputs for a channel to the LVDS inputs for a channel. As an example, to test Channel 1, connect DOUT1+ to RIN1+ and DOUT1 to RIN1 using SMB-to-SMB leads. A signal or pattern generator can be connected to IN1, and the output at the OUT1 test point (or the OUT1 connector) must match the input. The test setup is shown in Figure 3. Figure 2. Isolated LVDS Interface Circuit Logic signals can be applied to IN1 and IN2 and are isolated by the ADuM3442. The corresponding outputs of the ADuM3442 SIGNAL GENERATOR (the DIN1 and DIN2 test points) are connected to the ADN4663 LVDS driver to create LVDS signals on DOUT1+, DOUT1 and DOUT2+, DOUT2. OSCILLOSCOPE 3.3V POWER SUPPLY The ADN4664 LVDS receiver can receive LVDS signals on RIN1+, RIN1 and RIN2+, RIN2. The receiver outputs (the ROUT1, DOUT1 DOUT1+ GND2 ROUT2 test points) are connected to the ADuM3442 to isolate VDD2 GND1 VDD1 DOUT2+ the signals. The corresponding logic outputs from the ADuM3442 are OUT1 and OUT2. IN1 RIN2 DOUT2 IN2 The circuit is powered on the logic side by a connection to VDD1. RIN2+ OUT1 This supply can be 3.3 V or 5 V and powers the logic side of the OUT2 ADuM3442 (the signal isolation for the circuit) and provides RIN1+ EVALCN0256EBZ RIN1 power to the ADuM5000 , which provides an isolated supply for the bus side of the circuit. Figure 3. Transmit and Receive Channel 1 Test Setup The V output of the ADuM5000 provides the 3.3 V supply ISO required for the LVDS driver (ADN4663) and LVDS receiver (ADN4664) as well as the bus side of the ADuM3442. Rev. 0 Page 2 of 3 10386-002 10386-003