PDM Digital Input, Mono 2.4 W Class-D Audio Amplifier Data Sheet SSM2517 enables extremely low real-world power consumption from FEATURES digital audio sources with excellent audio performance. Using Filterless digital Class-D amplifier the SSM2517, audio can be transmitted digitally to the audio Pulse density modulation (PDM) digital input interface amplifier, significantly reducing the effect of noise sources such as 2.4 W into 4 load and 1.38 W into 8 load at 5.0 V supply GSM interference or other digital signals on the transmitted audio. with <1% total harmonic distortion plus noise (THD + N) The SSM2517 is capable of delivering 2.4 W of continuous output Available in 9-ball, 1.5 mm 1.5 mm, 0.5 mm pitch WLCSP power with <1% THD + N driving a 4 load from a 5.0 V supply. 92% efficiency into 8 at full scale Output noise: 43 V rms at 3.6 V, A-weighted The SSM2517 features a high efficiency, low noise modulation THD + N: 0.035% at 1 kHz, 100 mW output power scheme that requires no external LC output filters. The closed-loop, PSRR: 85 dB at 217 Hz, input referred with dither input three-level modulator design retains the benefits of an all-digital Quiescent power consumption: 10.4 mW amplifier, yet enables very good PSRR and audio performance. The (VDD = 1.8 V, PVDD = 3.6 V, 8 + 33 H load) modulation continues to provide high efficiency even at low output Pop-and-click suppression power and has an SNR of 96 dB. Spread-spectrum pulse density Configurable with PDM pattern inputs modulation is used to provide lower EMI-radiated emissions Short-circuit and thermal protection with autorecovery compared with other Class-D architectures. Smart power-down when PDM stop condition The SSM2517 has a four-state gain and sample frequency selection or no clock input detected pin that can select two different gain settings, optimized for 3.6 V 64 f or 128 f operation supporting 3 MHz and 6 MHz clocks S S and 5 V operation. This same pin also controls the internal digital DC blocking high-pass filter and static input dc protection filtering and clocking, which can be set for 64 f or 128 f input S S User-selectable ultralow EMI emissions mode sample rates to support both 3 MHz and 6 MHz PDM clock rates. Power-on reset (POR) The SSM2517 has a micropower shutdown mode with a typical Minimal external passive components shutdown current of 1 A for both power supplies. Shutdown is APPLICATIONS enabled automatically by gating input clock and data signals. A Mobile handsets standby mode can be entered by applying a designated PDM stop condition sequence. The device also includes pop-and-click sup- GENERAL DESCRIPTION pression circuitry. This suppression circuitry minimizes voltage The SSM2517 is a PDM digital input Class-D power amplifier glitches at the output when entering or leaving the low power that offers higher performance than existing DAC plus Class-D state, reducing audible noises on activation and deactivation. solutions. The SSM2517 is ideal for power sensitive applications, The SSM2517 is specified over the industrial temperature range such as mobile phones and portable media players, where system of 40 C to +85 C. It has built-in thermal shutdown and output noise can corrupt the small analog signal sent to the amplifier. short-circuit protection. It is available in a 9-ball, 1.5 mm 1.5 mm The SSM2517 combines an audio digital-to-analog converter wafer level chip scale package (WLCSP). (DAC), a power amplifier, and a PDM digital interface on a single chip. The integrated DAC plus analog - modulator architecture FUNCTIONAL BLOCK DIAGRAM VDD PVDD PGND SSM2517 POWER-ON CLOCKING POWER RESET CONTROL PDAT OUT+ - INPUT FILTERING/ FULL-BRIDGE CLASS-D INTERFACE DAC POWER STAGE MODULATOR PCLK OUT GAIN FS LRSEL Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09211-001SSM2517 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Master Clock............................................................................... 13 Applications....................................................................................... 1 Power Supplies............................................................................ 13 General Description ......................................................................... 1 Power Control............................................................................. 13 Functional Block Diagram .............................................................. 1 Power-On Reset/Voltage Supervisor ....................................... 13 Revision History ............................................................................... 2 System Gain/Input Frequency.................................................. 13 Specifications..................................................................................... 3 PDM Pattern Control ................................................................ 14 Digital Input Specifications......................................................... 4 EMI Noise.................................................................................... 14 PDM Interface Digital Timing Specifications .......................... 5 Output Modulation Description .............................................. 14 Absolute Maximum Ratings............................................................ 6 Applications Information .............................................................. 15 Thermal Resistance ...................................................................... 6 Layout .......................................................................................... 15 ESD Caution.................................................................................. 6 Power Supply Decoupling ......................................................... 15 Pin Configuration and Function Descriptions............................. 7 Outline Dimensions....................................................................... 16 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 16 Theory of Operation ...................................................................... 13 REVISION HISTORY 9/11Rev. A to Rev. B Changes to Table 3, Endnote 1, and Figure 2................................ 5 5/11Rev. 0 to Rev. A Changes to Table 6, LRSEL Pin Description................................. 7 10/10Revision 0: Initial Version Rev. B Page 2 of 16