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EVAL-SSM3515Z

EVAL-SSM3515Z electronic component of Analog Devices

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Audio IC Development Tools Eval Board for ssm3515

Manufacturer: Analog Devices
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1: USD 724.9023 ea
Line Total: USD 724.9

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EVAL-SSM3515Z
Analog Devices

1 : USD 771.3562

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EVAL-SSM3515Z
Analog Devices

1 : USD 718.8724

     
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31 W, Filterless, Class-D Digital Input Audio Amplifier Data Sheet SSM3515 FEATURES GENERAL DESCRIPTION Filterless digital input, mono Class-D amplifier The SSM3515 is a fully integrated, high efficiency, mono Class-D Operates from a single 4.5 V to 17 V supply audio amplifier with digital inputs. The application circuit 31.3 W output power, 17 V supply, and 4 load at 1% THD + N requires a minimum of external components and can operate 107 dB A-weighted signal-to-noise ratio from a single 4.5 V to 17 V supply. It can deliver 8.4 W of output 93.3% efficiency into 8 load at 12 V power into an 8 load or 15.8 W into an 4 load from a 12 V 2 I C control with up to 4 pin selectable slots/addresses power supply, or 31.3 W into an 4 load from a 17 V power Supports multiple serial data formats up to TDM16 supply, all with 1% THD + N. Digital interface supports sample rates from 8 kHz to 192 kHz The SSM3515 features a high efficiency, low noise modulation Flexible digital and analog gain adjustment scheme that requires no external LC output filters. This scheme Flexible supply monitoring AGC function provides high efficiency even at low output power. It operates 6.55 mA quiescent current with single 17 V PVDD supply with 92% efficiency at 7 W into an 8 load or 88% efficiency at Short-circuit and thermal protection, thermal warning 15 W into 4 from a 12 V supply. 20-ball, 1.8 mm 2.2 mm, 0.4 mm pitch WLCSP Spread spectrum pulse density modulation provides lower EMI Pop and click suppression radiated emissions compared with other Class-D architectures, User selectable ultralow EMI emissions mode particularly above 100 MHz. Power-on reset The digital input eliminates the need for an external digital-to- APPLICATIONS analog converter (DAC). The SSM3515 has a micropower Notebooks shutdown mode with a typical shutdown current of 39 nA at Portable electronics the 12 V PVDD supply. The device also includes pop and click Home audio suppression circuitry that minimizes voltage glitches at the output during turn on and turn off. 2 The SSM3515 operates with or without an I C control interface. The SSM3515 is specified over the commercial temperature range (40 C to +85 C). It has built in thermal shutdown and output short-circuit protection. It is available in a halide-free, 20-ball, 1.8 mm 2.2 mm wafer-level chip scale package (WLCSP). FUNCTIONAL BLOCK DIAGRAM 5V 1.8V VREG50/AVDD VREG18/DVDD AGND REG EN ADDR SCL 2 I C BST+ SDA BCLK FULL - TDM BRIDGE 2 DAC OUT+ VOLUME CLASS-D FSYNC I S POWER MODULATOR INPUT STAGE OUT SDATA BST SSM3515 PVDD PGND Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 13327-001SSM3515 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 EMI Noise .................................................................................... 24 Applications ....................................................................................... 1 Output Modulation Description .............................................. 24 General Description ......................................................................... 1 Faults and Limiter Status Reporting ........................................ 25 Functional Block Diagram .............................................................. 1 VBAT Sensing ............................................................................. 25 Revision History ............................................................................... 2 Limiter and Battery Tracking Threshold Control .................. 25 Specif icat ions ..................................................................................... 3 Layout .......................................................................................... 28 Digital Timing Characteristics ................................................... 6 Bootstrap Capacitors.................................................................. 28 Absolute Maximum Ratings ............................................................ 8 Power Supply Decoupling ......................................................... 28 Thermal Resistance ...................................................................... 8 Register Summary .......................................................................... 29 ESD Caution .................................................................................. 8 Register Details ............................................................................... 30 Pin Configuration and Function Descriptions ............................. 9 Power Control Register ............................................................. 30 Typical Performance Characteristics ........................................... 10 Gain and Edge Control Register............................................... 30 Theory of Operation ...................................................................... 19 DAC Control Register ................................................................ 31 O ver vie w ...................................................................................... 19 DAC Volume Control Register ................................................. 32 Power Supplies ............................................................................ 19 SAI Control 1 Register ............................................................... 33 Power-Up Sequence ................................................................... 19 SAI Control 2 Register ............................................................... 34 Power-Down Operation ............................................................ 19 Battery Voltage Output Register ............................................... 35 REG EN Pin Setup and Control .............................................. 19 Limiter Control 1 Register ........................................................ 35 ADDR Pin Setup and Control .................................................. 20 Limiter Control 2 Register ........................................................ 36 Clocking ....................................................................................... 20 Limiter Control 3 Register ........................................................ 37 Digital Audio Serial Interface ....................................................... 21 Status Register ............................................................................. 37 2 Stereo (I S/Left Justified) Operating Mode ............................. 21 Fault Control Register ................................................................ 38 TDM Operating Mode ............................................................... 21 Typical Application Circuit ........................................................... 40 2 I C Control .................................................................................. 21 Outline Dimensions ....................................................................... 41 Analog and Digital Gain ............................................................ 24 Ordering Guide .......................................................................... 41 Pop and Click Suppression ........................................................ 24 REVISION HISTORY 1/2017Rev. 0 to Rev. A Changes to Figure 2 and Table 5 ..................................................... 6 6/2015Revision 0: Initial Version Rev. A Page 2 of 41

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