Data Sheet ACPL-0873T Automotive 3-Channel Digital Filter for Sigma-Delta Modulators Description Features The Broadcom ACPL-0873T is a 3-channel digital filter Qualified to AEC-Q100 Grade 1 Test Guidelines designed specifically for Second Order Sigma Delta Direct interface between Isolated Sigma-Delta Modulators in voltage and current sensing. Each input Modulator (ACPL-C797T/C799T) and MCU/DSP channel can receive an independent Sigma-Delta (-) Three individual digital filters modulator bit stream. The bit streams are processed by Synchronizing sampling time three individual digital decimation filters. Features of the Fast over-range detection 2 digital filter include four decimation ratios for Sinc mode Offset calibration 3 and three decimation ratios for Sinc mode, offset Channel 1 MCLK clock detection at power up calibration, and fast over-range detection. Synchronization Programmable input configuration of inputs from three channels is done internally by the filter SPI-compatible interface alignment. Compact surface-mount QFN-20 5 mm 5 mm The ACPL-0873T outputs an over-range signal for three Specifications channels, signaling over-voltage/current conditions. Operating temperature 40C to 125C Programmable through SPI compatible interface, ACPL- SPI clock frequency up to 17 MHz 0873T can directly connect to a microcontroller to output 16 bits digital filter data and write/read filter registers. Modulator clock frequency up to 25 MHz Applications Automotive electric motor phase and rail current sensing Automotive DC/DC converter current sensing Automotive AC-DC charger current sensing Automotive battery current sensing General voltage or current sensing Broadcom ACPL-0873T-DS104 January 21, 2020ACPL-0873T Data Sheet Automotive 3-Channel Digital Filter for Sigma-Delta Modulators Schematic Diagram and Package Pin Out Figure 1: Schematic Diagram and Package Pin Out NOTE: 0.1-F and 1-F bypass capacitors between VDD and GND are recommended. Table 1: Pin Function Description Pin No. Pin Name Description Type 1 MCLK1 Channel 1 Clock. Input 2 MDAT1 Channel 1 Data. Input Data on MDAT1 is clocked in on the rising edge of MCLK1. Input 3 MCLK2 Channel 2 Clock. Input 4 MDAT2 Channel 2 Data. Input Data on MDAT2 is clocked in on the rising edge of MCLK2. Input 5 NC Not connected. 6 NC Not connected. 7CS Chip Select, Active Low of Chip Select for SPI interface and digital filter conversion start on the falling Input edge of CS. 8 SCLK SPI Clock input. Input 9 GND Ground. Power Input 10 MOSI SPI data Master Out Slave In. Input 11 MISO SPI data Master In Slave Out. Output 12 OC Over-range Condition. Output 13 DR Data Ready. Output 1. DR pin High indicates Digital Filter data conversion ready. 2. DR pin is automatically cleared to Low when CS goes high. 14 INT Interrupt, Active Low. Output 15 NC Not connected. 16 NC Not connected. 17 RST Reset. Active Low, period 100 s at least. Input 18 VDD Power Supply. Power Input 19 MDAT3 Channel 3 Data. Input Data on MDAT3 is clocked in on the rising edge of MCLK3. Input 20 MCLK3 Channel 3 Clock. Input Broadcom ACPL-0873T-DS104 2