AFBR-5972BZ

AFBR-5972Z Compact 650nm Transceiver with Compact Versatile-Link connector for Fast Ethernet over POF Data Sheet Description Features The AFBR-5972Z Transceiver provides the system designer Compatible to IEEE 802.3 100BASE-FX PMA using POF with the ability to implement Fast Ethernet (100 Mbps) PMD over standard bandwidth 0.50.05 NA POF. It features a Link lengths up to 50m POF (NA0.5) or 70m POF (NA0.3) very compact design and has a form factor similar to the Compact foot print UTP connector. This transceiver features a new compact Versatile-Link duplex connector AFBR-4526Z and is com- 3.3V operation patible with existing simplex Versatile-Link connectors . LVPECL input and output data connections This product is lead free and compliant with RoHS. LVPECL signal detect output Temperature range -40C to 85C Transmitter Applications The transmitter contains a 650nm LED with an integrated driver. The LED driver operates at 3.3 V. It receives a LVPE- Industrial Ethernet and Fast Ethernet over polymer CL/LVDS electrical input, and converts it into a modulated optical fiber PMD current driving the LED. The LED is packaged in an optical Networking in harsh environments like factory subassembly, part of the transmitter section. The optical automation or power generation and distribution subassembly couples the output optical power efficiently into POF fiber. Supporting various Ethernet Fieldbus protocols Receiver The receiver utilizes a Si PIN photodiode. The PIN pho- Di erential todiode is packaged in an optical sub-assembly, part of Data Output Integrated the receiver section. This optical subassembly couples the Receiver optical power efficiently from POF fiber to the receiving Signal PIN. The integrated IC operates at 3.3 V and converts the PIN Photodiode Detect Output photocurrent into LVPECL electrical output. Package LED Driver Di erential The transceiver package consists of three basic elements Data Input LED two opto-electical subassemblies and the housing as illus- trated in the block diagrams in Figure 1. The package out- line drawing and pin-outs are shown in Figures 2 and 5. Figure 1. Block diagram. Patent - www.avagotech.com/patents S TANDOF F AR E A (2 x 0.65 x 1.03) 8.89 8.66 2 4 6 8 NOT E S : 6.35 1 3 5 7 1) Dimension: mm 2) G eneral tolerance: 0.05 3.18 3.05 3) R ecommended P C B Thickness 1.57 0.05 4) P in description 0 0 MOUNT P OS T P IN F UNC UNP LAT E D (2x) 1 T D+ 2 T D- +0.1 3.73 3.2 (2x) 3 T xV cc 4 G ND 5 R xVcc S T ANDOF F 6 S D AR E A (4 x 1.9 x 1) 7 R D+ T op View 8 R D- F ront Figure 2. PCB footprint and Pin-out diagram. The opto-electrical subassemblies utilize a high volume Pin 4 GND: common ground pin. Directly connect this pin assembly process together with low cost lens elements to the signal ground plane of the host board. which result in a cost effective building block. It consists Pin 5 RX Vcc: receiver power supply pin. Provide +3.3 V DC of the active III-V devices, IC chips and various surface via a receiver power supply filter circuit. Locate the power mounted passive components. supply filter circuit as close as possible to the Rx Vcc pin There are eight signal pins, four EMI shield solder posts Pin 6. SD: signal detect pin. If an optical signal is present and two mounting posts, which exit the bottom of the at the optical input, SD output is a logic 1. Absence of an housing. The solder posts are isolated from the internal optical input signal results in a logic 0 output. This pin circuit of the transceiver and are to be connected to chas- can be used to drive a LVPECL input of an upstream circuit, sis ground. The mounting posts are to provide mechanical such as Signal Detect input or Loss of Signalbar. strength to hold the transceiver to the application board. Pin 7 RData+: receiver data out. This data line is a 3.3V LVPECL compatible differential line which should be prop - Pin Descriptions erly terminated. Pin 1 TData+: transmitter data in. This input is a 3.3V LVPE- Pin 8 RData-: receiver data out negative. This data line is a CL/LVDS compatible differential line. 3.3V LVPECL compatible differential line which should be Pin 2 TData-: transmitter data in negative. This input is a properly terminated. When SD is de-asserted, RData+ will 3.3V LVPECL/LVDS compatible differential line. be set to logic 0 and RData- will be set to logic 1. Pin 3 TX Vcc: transmitter power supply pin. Provide +3.3 Shield: This is to be connected to the equipment chassis V DC via a transmitter power supply filter circuit. Locate ground. the power supply filter circuit as close as possible to the Tx Vcc pin. 2 +0.1 0.9 (8x) S HIE LD G ND +0.1 1.6 (2x) 7.78 7.77 6.7 5.76 4.44 3.17 2.45 1.9 0.63 0 0 0.64 2.45 1.91 3.18 4.45 5.76 6.7 7.77 7.78