PEX 8649, PCI Express Gen 2 Switch, 48 Lanes, 12 Ports Highlights The ExpressLane PEX 8649 device offers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their PEX 8649 General Features o 48-lane, 12-port PCIe Gen2 switch respective endpoints via scalable, high bandwidth, non-blocking - Integrated 5.0 GT/s SerDes 2 interconnection to a wide variety of applications including servers, o 27 x 27mm , 676-ball FCBGA package o Typical Power: 6.7 Watts storage systems, and communications platforms. The PEX 8649 is well suited for fan-out, aggregation, and peer-to-peer applications. PEX 8649 Key Features o Standards Compliant Multi-Host Architecture - PCI Express Base Specification, r2.0 The PEX 8649 employs an enhanced version of PLXs field tested PEX 8648 (backwards compatible w/ PCIe PCIe switch architecture, which allows users to configure the device in legacy r1.0a/1.1) - PCI Power Management Spec, r1.2 single-host mode or multi-host mode with up to four host ports capable of 1+1 - Microsoft Vista Compliant (one active & one backup) or N+1 (N active & one backup) host failover. This - Supports Access Control Services powerful architectural enhancement enables users to build PCIe based systems - Dynamic link-width control to support high-availability, failover, redundant and clustered systems. - Dynamic SerDes speed control o High Performance performancePAK High Performance & Low Packet Latency 9 Read Pacing (bandwidth throttling) The PEX 8649 architecture supports packet cut-thru with a maximum 9 Multicast latency of 176ns (x16 to x16). This, combined with large packet memory, 9 Dynamic Buffer/FC Credit Pool flexible common buffer/FC credit pool and non-blocking internal switch - Non-blocking switch fabric - Full line rate on all ports architecture, provides full line rate on all ports for performance-hungry - Packet Cut-Thru with 176ns max packet applications such as servers and switch fabrics. The low latency enables latency (x16 to x16) applications to achieve high throughput and performance. In addition to low - 2KB Max Payload Size latency, the device supports a packet payload size of up to 2048 bytes, o Flexible Configuration enabling the user to achieve even higher throughput. - Ports configurable as x1, x2, x4, x8, x16 - Registers configurable with strapping 2 pins, EEPROM, I C, or host software Data Integrity - Lane and polarity reversal The PEX 8649 provides end-to-end CRC (ECRC) protection and Poison bit - Compatible with PCIe 1.0a PM support to enable designs that require end-to-end data integrity. PLX also o Multi-Host & Fail-Over Support - Configurable Non-Transparent (NT) port supports data path parity and memory (RAM) error correction circuitry - Failover with NT port throughout the internal data paths as packets pass through the switch. - Up to Four upstream/Host ports with 1+1 or N+1 failover to other upstream Flexible Configuration ports The PEX 8649s 12 ports can be o Quality of Service (QoS) - Eight traffic classes per port configured to lane widths of x1, x2, x4, - Weighted round-robin source x8, or x16. Flexible buffer allocation, port arbitration along with the device s flexible packet o Reliability, Availability, Serviceability flow control, maximizes throughput visionPAK for applications where more traffic 9 Per Port Performance Monitoring Per port payload & header counters flows in the downstream, rather than 9 SerDes Eye Capture upstream, direction. Any port can be 9 Error Injection and Loopback designated as the upstream port, which - 3 Hot Plug Ports with native HP Signals 2 can be changed dynamically. Figure 1 - All ports hot plug capable thru I C shows some of the PEX 8649s (Hot Plug Controller on every port) - ECRC and Poison bit support common port configurations in legacy - Data Path parity Single-Host mode. - Memory (RAM) Error Correction - INTA and FATAL ERR signals - Advanced Error Reporting - Port Status bits and GPIO available Per port error diagnostics - JTAG AC/DC boundary scan PLX Technology, www.plxtech.com Page 1 of 1 5/14/2009, Version 1.1 PEX 8649, PCI Express Gen 2 Switch, 48 Lanes, 12 Ports The PEX 8649 can also be configured in Multi-Host mode Multi-Host & Failover Support where users can choose up to four ports as host/upstream In Multi-Host mode, PEX 8649 can be configured with up ports and assign a desired number of downstream ports to to four upstream host ports, each with its own dedicated each host. In Multi-Host mode, a virtual switch is created downstream ports. The device can be configured for 1+1 for each host port and its associated downstream ports redundancy or N+1 redundancy. The PEX 8649 allows the inside the device. The traffic between the ports of a virtual hosts to communicate their status to each other via special switch is completely isolated from the traffic in other door-bell registers. In failover mode, if a host fails, the virtual switches. Figure 2 illustrates some configurations host designated for failover will disable the upstream port of the PEX 8649 in Multi-Host mode where each ellipse attached to the failing host and program the downstream represents a virtual switch inside the device. ports of that host to its own domain. Figure 4a shows a two host system in Multi-Host mode with two virtual switches The PEX 8649 x8 x8 x8 x4 x4 inside the device and Figure 4b shows Host 1 disabled also provides after failure and Host 2 having taken over all of Host 1s several ways to end-points. configure its PEX 8649PEX 8649 PEX 8649PEX 8649 PEX 86PEX 864949 PEX 8649PEX 8649 Host 1Host 1Host 1Host 1 Host 2Host 2Host 2Host 2 Host 1Host 1Host 1Host 1 Host 2Host 2Host 2Host 2 registers. The device can be PEX 8649 PEX 8649 PEX 8649 PEX 8649 configured 3 x8 2 x4 2 x8 2 x4 2 x4 through strapping 3 x4s 4 x4s 2 pins, I C EndEnd End End EnEnd d EnEnd d EnEnd d EnEnd d EndEnd End End EndEnd End End EnEnd d EnEnd d EnEnd d EnEnd d EndEnd End End interface, host PoPoiinntt PointPoint PointPoint PointPoint PointPoint PoPoiinntt PoPoiinntt PoPoiinntt PoPoiinntt PointPoint PointPoint PointPoint PointPoint PoPoiinntt PoPoiinntt PoPoiinntt software, or an Figure 4a. Multi-Host Figure 4b. Multi-Host Fail-Over optional serial PEPEPEXPEXX 8649X 8649 8649 8649 PEX 86PEX 86PEPEX 8649X 86494949 EEPROM. This Hot Plug for High Availability allows for easy Hot plug capability allows users to replace hardware 8 x4s debug during the 9 x4s modules and perform maintenance without powering down Figure 2. Common Multi-Host Configurations development the system. The PEX 8649 hot plug capability feature phase, performance monitoring during the operation phase, makes it suitable for High Availability (HA) and driver or software upgrade. applications. Three downstream ports include a Standard Hot Plug Controller. If the PEX 8649 is used in an Dual-Host & Failover Support application where one or more of its downstream ports In Single-Host mode, the PEX 8649 supports a Non- connect to PCI Express slots, each ports Hot Plug Transparent (NT) Port, which enables the Controller can be used to manage the hot-plug event of its implementation of dual- associated slot. Every port on the PEX 8649 is equipped host systems for with a hot-plug control/status register to support hot-plug 2 redundancy and host capability through external logic via the I C interface. failover capability. The NT port allows systems SerDes Power and Signal Management to isolate host memory The PEX 8649 supports software control of the SerDes domains by presenting outputs to allow optimization of power and signal strength the processor subsystem in a system. The PLX SerDes implementation supports as an endpoint rather four levels of power off, low, typical, and high. The than another SerDes block also supports loop-back modes and memory system. advanced reporting of error conditions, which enables Base address efficient management of the entire system. registers are used to translate addresses doorbell registers are used to send interrupts between the address domains and scratchpad registers (accessible by both CPUs) allow inter-processor communication (see Figure 3). PLX Technology, www.plxtech.com Page 2 of 2 5/14/2009, Version 1.1