CS42426 114 dB, 192-kHz 6-Ch CODEC with PLL Features General Description Six 24-bit D/A, two 24-bit A/D Converters The CS42426 provides two analog-to-digital and six digital-to-analog delta-sigma converters, as well as an 114 dB DAC / 114 dB ADC Dynamic Range integrated PLL. -100 dB THD+N The CS42426 integrated PLL provides a low-jitter sys- System Sampling Rates up to 192 kHz tem clock. The internal stereo ADC is capable of independent channel gain control for single-ended or Integrated Low-Jitter PLL for Increased System differential analog inputs. All six channels of DAC pro- Jitter Tolerance vide digital volume control and differential analog PLL Clock or System Clock Selection outputs. The general-purpose outputs may be driven 7 Configurable General-Purpose Outputs high or low, or mapped to a variety of DAC mute con- trols or ADC overflow indicators. ADC High-Pass Filter for DC Offset Calibration The CS42426 is ideal for audio systems requiring wide Expandable ADC Channels and One-Line dynamic range, negligible distortion and low noise, such Mode Support as A/V receivers, DVD receivers, and digital speakers. Digital Output Volume Control with Soft Ramp The CS42426 is available in a 64-pin LQFP package in Digital 15 dB Input Gain Adjust for ADC Commercial (-10 to +70 C) grades. The CDB42428 Customer Demonstration board is also available for de- Differential Analog Architecture vice evaluation. Refer to Ordering Information on Supports Logic Levels between 1.8 V and 5 V page 71. VA AGND REFGND VQ FILT+ OMCK RMCK LPFLT VLC DGND VD GPO1 INT GPO2 Mult/Div GPO3 RST Control GPO4 GPO AD0/CS GPO5 Port AD1/CDIN GPO6 SDA/CDOUT Internal Voltage Mute GPO7 SCL/CCLK Reference PLL MUTEC ADCIN1 ADCIN2 AINL+ ADC 1 Digital Filter ADC ADC SDOUT Gain & Clip AINL- Serial ADC LRCK Audio AINR+ ADC 2 Digital Filter Gain & Clip Port AINR- ADC SCLK VLS AOUTA1+ DAC 1 AOUTA1- DAC LRCK AOUTB1+ DAC 2 DAC SCLK AOUTB1- DAC SDIN1 AOUTA2+ DAC 3 AOUTA2- DAC SDIN2 DAC SDIN3 AOUTB2+ DAC 4 AOUTB2- AOUTA3+ DAC 5 AOUTA3- AOUTB3+ DAC 6 AOUTB3- Copyright Cirrus Logic, Inc. 2014 MAR 14 (All Rights Reserved) DS604F2 CS42426 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 SPECIFIED OPERATING CONDITIONS ............................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 6 ANALOG INPUT CHARACTERISTICS .................................................................................................. 7 A/D DIGITAL FILTER CHARACTERISTICS .......................................................................................... 8 ANALOG OUTPUT CHARACTERISTICS .............................................................................................. 9 D/A DIGITAL FILTER CHARACTERISTICS ........................................................................................ 10 SWITCHING CHARACTERISTICS ......................................................................................................11 SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT ........................................... 12 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT .......................................... 13 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 14 DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 15 2. PIN DESCRIPTIONS ............................................................................................................................ 16 3. TYPICAL CONNECTION DIAGRAMS ..............................................................................................18 4. APPLICATIONS ................................................................................................................................... 20 4.1 Overview ......................................................................................................................................... 20 4.2 Analog Inputs .................................................................................................................................. 20 4.2.1 Line-Level Inputs ................................................................................................................... 20 4.2.2 High-Pass Filter and DC Offset Calibration ........................................................................... 21 4.3 Analog Outputs ............................................................................................................................... 21 4.3.1 Line-Level Outputs and Filtering ........................................................................................... 21 4.3.2 Interpolation Filter .................................................................................................................. 21 4.3.3 Digital Volume and Mute Control ........................................................................................... 22 4.3.4 ATAPI Specification ............................................................................................................... 22 4.4 Clock Generation ............................................................................................................................ 23 4.4.1 PLL and Jitter Attenuation ..................................................................................................... 23 4.4.2 OMCK System Clock Mode ...................................................................................................24 4.4.3 Master Mode ......................................................................................................................... 24 4.4.4 Slave Mode ........................................................................................................................... 24 4.5 Digital Interfaces ............................................................................................................................. 25 4.5.1 Serial Audio Interface Signals ............................................................................................... 25 4.5.2 Serial Audio Interface Formats .............................................................................................. 27 4.5.3 ADCIN1/ADCIN2 Serial Data Format .................................................................................... 30 4.5.4 One-Line Mode (OLM) Configurations .................................................................................. 31 4.5.4.1 OLM Config 1 ........................................................................................................... 31 4.5.4.2 OLM Config 2 ........................................................................................................... 32 4.5.4.3 OLM Config 3 ........................................................................................................... 33 4.5.4.4 OLM Config 4 ........................................................................................................... 34 4.6 Control Port Description and Timing ............................................................................................... 35 4.6.1 SPI Mode ............................................................................................................................... 35 4.6.2 IC Mode ................................................................................................................................ 36 4.7 Interrupts ........................................................................................................................................ 37 4.8 Reset and Power-Up ...................................................................................................................... 38 4.9 Power Supply, Grounding, and PCB Layout .................................................................................. 38 5. REGISTER QUICK REFERENCE ........................................................................................................ 39 6. REGISTER DESCRIPTION .................................................................................................................. 42 6.1 Memory Address Pointer (MAP) ..................................................................................................... 42 6.2 Chip I.D. and Revision Register (address 01h) (Read Only) .......................................................... 42 6.3 Power Control (address 02h) .......................................................................................................... 43 6.4 Functional Mode (address 03h) ...................................................................................................... 43 6.5 Interface Formats (address 04h) .................................................................................................... 45 6.6 Misc Control (address 05h) ............................................................................................................ 46 2 DS604F2