CS53L30 Low-Power Quad-Channel Microphone ADC with TDM Output Analog Input and ADC Features System Features 91-dB dynamic range (A-weighted) 0-dB gain Native (no PLL required) support for 6-/12-MHz, 6.144-/ 12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz master 84-dB THD+N 0-dB gain clock rates and 8- to 48-kHz audio sample rates Four fully differential inputs: Four analog mic/line inputs Master or Slave Mode. Clock dividers can be used to Four analog programmable gain amplifiers generate common audio clocks from single-master clock input. 6 to +12 dB, in 0.5-dB steps Low power consumption +10 or +20 dB boost for mic input Less than 4.5-mW stereo (16 kHz) analog mic record Four mic bias generators Less than 2.5-mW mono (8 kHz) analog mic record MUTE pin for quick mic mute and programmable quick power down Selectable mic bias and digital interface logic voltages High-speed (400-kHz) IC control port Digital Processing Features Available in 30-ball WLCSP and 32-pin QFN Volume control, mute, programmable high-pass filter, noise gate Applications Two digital mic (DMIC) interfaces Voice-recognition systems Digital Output Features Advanced headsets and telephony systems Voice recorders Two DMIC SCLK generators Digital cameras and video cameras 2 Four-channel I S output or TDM output. Four CS53L30s can be used to output 16 channels of 24-bit 16-kHz sample rate data on a single TDM line. VA CS53L30 LDO VD Digital Processing IN1+/DMIC1 SD IN1 + ADC1A HPF, Noise + Gate, Volume, 2 Mute IN2+ + IN2 ADC1B + 6 to +12 dB, +10 or +20 dB MCLK INT 0.5 dB steps IN3+/DMIC2 SD IN3 + ADC2A + HPF, Noise Gate, Volume, Mute 2 IN4+ 4 + IN4 ADC2B + Synchronous 6 to +12 dB, SRC +10 or +20 dB MCLK INT 0.5 dB steps MCLK INT MIC 1 BIAS MIC1 Bias Control Port Clock Divider Audio DMIC MIC 2 BIAS Synchronizer Serial Port MIC2 Bias MIC3 BIAS MIC3 Bias MIC4 BIAS MIC4 Bias Level Shifters SYNC RESET DMIC1 SCLK Control MCLK Serial Port Port DMIC2 SCLK VP MUTE Copyright Cirrus Logic, Inc. 20132019 DS992F3 (All Rights Reserved) DEC 19 CS53L30 General Description The CS53L30 is a high-performance, low-power, quad-channel ADC. It is designed for use in multiple-mic applications while consuming minimal board space and power. The flexible ADC inputs can accommodate four channels of analog mic or line-input data in differential, pseudodifferential, or single-ended mode, or four channels of digital mic data. The analog input path includes a +10- to +20-dB boost and a 6- to +12-dB PGA. Digital mic data bypasses the analog gain circuits and is fed directly to the decimators. Four mic bias generators are integrated into the device. The device also includes two digital mic serial clock outputs. The CS53L30 includes several digital signal processing features such as high-pass filters, noise gate, and volume control. 2 The device can output its four channels of audio data over two I S ports or a single TDM port. Additionally, up to four CS53L30s can be used to output up to 16 channels of data over a single TDM line. This is done by setting the appropriate frame slots for each device, and each device then alternates between outputting data and setting the output pin to high impedance. The CS53L30 can operate as a serial port clock master or slave. In Master Mode, clock dividers are used to generate the internal master clock and audio clocks from either the 6-/12-MHz, 6.144-/12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz master clock. The device is powered from VA, a 1.8-V nominal supply and VP, a typical battery supply. An internal LDO on the VA supply powers the devices digital core. The VP supply powers the mic bias generators and the AFE. 2 The CS53L30 is controlled by an I C control port. A reset pin is also included. The device is available in a 30-ball 0.4-mm pitch WLCSP package and 32-pin 5 x 5-mm QFN package. 2 DS992F3