WM8214SCDS/V

WM8214 40MSPS 16-bit CCD Digitiser DESCRIPTION FEATURES 16-bit ADC The WM8214 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals 40MSPS conversion rate from CCD sensors or Contact Image Sensors (CIS) at pixel Low power 390mW typical sample rates of up to 40MSPS. 3.3V single supply operation The device includes three analogue signal processing Single, 2 or 3 channel operation channels each of which contains Reset Level Clamping, Correlated double sampling Correlated Double Sampling and Programmable Gain and Programmable gain (9-bit resolution) Offset adjust functions. Three multiplexers allow single Programmable offset adjust (8-bit resolution) channel processing. The output from each of these channels Flexible clamp control with programmable clamp voltage is time multiplexed into a single high-speed 16-bit Analogue to Digital Converter. The digital output data is available in 8- Flexible timing, can be made compatible with WM819X bit wide multiplexed format and there is also an optional and WM815X parts. single byte output mode, or 4-bit multiplexed LEGACY 8-bit wide multiplexed data output format mode. 8-bit only output mode An internal 4-bit DAC is supplied for internal reference level 4-bit LEGACY multiplexed nibble mode generation. This may be used during CDS to reference CIS Internally generated voltage references signals or during Reset Level Clamping to clamp CCD 28-lead SSOP package, pin compatible with WM8199 signals. An external reference level may also be supplied. Serial control interface ADC references are generated internally, ensuring optimum performance from the device. APPLICATIONS Using an analogue supply voltage of 3.3V and a digital High speed USB2.0 compatible scanners interface supply of 3.3V, the WM8214 typically only Multi-function peripherals consumes 390mW. High-performance CCD sensor interface Digital Copiers BLOCK DIAGRAM VRLC/VBIAS RSMP VSMP MCLK AVDD DVDD1 DVDD2 VRT VRX VRB WM8214 CLMP R V TIMING CONTROL S S VREF/BIAS R 8 M OFFSET OEB U G DAC X B RINP RLC CDS + PGA + I/P SIGNAL R M 9 POLARITY U G OP 0 ADJUST X B OP 1 OP 2 16- DATA M OP 3 GINP RLC CDS BIT O/P + PGA + U OP 4 ADC PORT X 8 OP 5 OFFSET 9 I/P SIGNAL OP 6 DAC POLARITY OP 7 /SDO ADJUST BINP RLC CDS + PGA + 8 OFFSET 9 I/P SIGNAL DAC POLARITY CONFIGURABLE SEN ADJUST SERIAL SCK CONTROL RLC 4 SDI INTERFACE DAC DGND AGND1 AGND2 Rev 4.5 Copyright Cirrus Logic, Inc., 2002 2020 JAN 2020 WM8214 TABLE OF CONTENTS DESCRIPTION ................................................................................................................ 1 FEATURES ..................................................................................................................... 1 APPLICATIONS .............................................................................................................. 1 BLOCK DIAGRAM ......................................................................................................... 1 TABLE OF CONTENTS .................................................................................................. 2 PIN CONFIGURATION ................................................................................................... 3 ORDERING INFORMATION ........................................................................................... 3 PIN DESCRIPTION ......................................................................................................... 4 ABSOLUTE MAXIMUM RATINGS ................................................................................. 5 RECOMMENDED OPERATING CONDITIONS .............................................................. 6 THERMAL PERFORMANCE .......................................................................................... 6 ELECTRICAL CHARACTERISTICS .............................................................................. 7 INPUT VIDEO SAMPLING ......................................................................................................... 9 SERIAL INTERFACE ............................................................................................................... 11 INTERNAL POWER ON RESET CIRCUIT ................................................................... 12 DEVICE DESCRIPTION ............................................................................................... 14 INTRODUCTION ...................................................................................................................... 14 INPUT SAMPLING ................................................................................................................... 14 RESET LEVEL CLAMPING (RLC) ........................................................................................... 15 CDS/NON-CDS PROCESSING ............................................................................................... 19 OFFSET ADJUST AND PROGRAMMABLE GAIN .................................................................. 19 ADC INPUT BLACK LEVEL ADJUST ...................................................................................... 20 OVERALL SIGNAL FLOW SUMMARY .................................................................................... 21 CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT ................................................. 22 OUTPUT FORMATS ................................................................................................................ 23 REFERENCES ......................................................................................................................... 23 POWER MANAGEMENT ......................................................................................................... 24 LINE-BY-LINE OPERATION .................................................................................................... 24 CONTROL INTERFACE ........................................................................................................... 24 NORMAL OPERATING MODES .............................................................................................. 26 LEGACY MODE INFORMATION ............................................................................................. 27 LEGACY OPERATING MODES ............................................................................................... 28 LEGACY MODE TIMING DIAGRAMS ..................................................................................... 29 DEVICE CONFIGURATION .......................................................................................... 31 REGISTER MAP ...................................................................................................................... 31 REGISTER MAP DESCRIPTION ............................................................................................. 32 APPLICATIONS INFORMATION ................................................................................. 37 RECOMMENDED EXTERNAL COMPONENTS ...................................................................... 37 RECOMMENDED EXTERNAL COMPONENT VALUES ......................................................... 37 PACKAGE DIMENSIONS ............................................................................................. 38 IMPORTANT NOTICE .................................................................................................. 39 REVISION HISTORY .................................................................................................... 40 2 Rev 4.5