WM8224CSEFL

WM8224 w 60MSPS 3-Channel AFE with Multiple Device Operation and Programmable Automatic Black Level Calibration DESCRIPTION FEATURES 12 or 16-bit ADC, 40MSPS conversion rate The WM8224 is an analogue front end/digitiser IC which processes and digitises the analogue output signals from 8 or 10-bit ADC, 60MSPS conversion rate CCD sensors or Contact Image Sensors (CIS) at pixel Low power 360 mW typical sample rates of up to 60MSPS. 3.3V single supply operation The device includes three analogue signal processing 3 channel operation channels each of which contains Reset Level Clamping, Daisy Chain feature for multiple device use Correlated Double Sampling and Programmable Gain and Correlated double sampling Offset adjust functions. The output from each of these Programmable gain (9-bit resolution) channels is time multiplexed into a single high-speed 16-bit Programmable offset adjust (8-bit resolution) Analogue to Digital Converter. The digital data is available in a variety of output formats via the flexible data port. Flexible clamp timing Programmable clamp voltage An internal 4-bit DAC is supplied for internal reference level Internally generated voltage references generation. This may be used during CDS to reference CIS signals or during Clamping to clamp CCD signals. An Automatic Black Level Calibration external reference level may also be supplied. ADC 32-lead QFN package references are generated internally, ensuring optimum Serial control interface performance from the device. A programmable automatic Black-Level Calibration function is available to adjust the DC offset of the output data. A APPLICATIONS daisy chain feature allows multiple devices to operate Digital Copiers together using the same control interface and output data bus. USB2.0 compatible scanners Multi-function peripherals High-speed CCD/CIS sensor interface BLOCK DIAGRAM VRT VRX VRB VRLC/VBIAS RSMP VSMP MCLK AVDD DVDD CLMP R V TIMING CONTROL S S WM8224 VREF/BIAS OEB RINP OP 0 + PGA + RLC CDS OP 1 I/P SIGNAL OFFSET POLARITY OP 2 DAC ADJUST OP 3 OP 4 M 16- DATA OP 5 GINP + PGA + U RLC BIT O/P CDS + OP 6 X ADC PORT OFFSET I/P SIGNAL OP 7 DAC POLARITY OP 8 ADJUST OP 9 OP 10 OP 11 /SDO BINP + PGA + RLC CDS OFFSET DSLCT I/P SIGNAL DAC POLARITY ADJUST SERIAL SEN CONTROL RLC SCK INTERFACE BLACK LEVEL DAC SDI CALIBRATION AGND1 AGND2 DGND WOLFSON MICROELECTRONICS plc Production Data, September 2013, Rev 4.2 Copyright 2013 Wolfson Microelectronics plc. WM8224 Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS ..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 4 ORDERING INFORMATION .................................................................................. 4 PIN DESCRIPTION ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ........................................................................ 6 RECOMMENDED OPERATING CONDITIONS ..................................................... 6 THERMAL PERFORMANCE ................................................................................. 6 ELECTRICAL CHARACTERISTICS ..................................................................... 7 40MHZ OPERATION ....................................................................................................... 7 60MHZ OPERATION ....................................................................................................... 7 GENERAL CHARACTERISTICS ..................................................................................... 9 INPUT VIDEO SAMPLING ............................................................................................ 11 CDS MODE (CDS=1) .................................................................................................... 11 NON-CDS MODE (CDS=0) ........................................................................................... 12 OUTPUT DATA TIMING ................................................................................................ 14 SERIAL INTERFACE ..................................................................................................... 15 INTERNAL POWER ON RESET CIRCUIT .......................................................... 16 DEVICE DESCRIPTION ...................................................................................... 18 INTRODUCTION ........................................................................................................... 18 CONFIGURABLE RESOLUTION OF ADC .................................................................... 18 INPUT SAMPLING ........................................................................................................ 18 RESET LEVEL CLAMPING (RLC) ................................................................................ 19 CDS/NON-CDS PROCESSING..................................................................................... 21 OFFSET ADJUST AND PROGRAMMABLE GAIN ........................................................ 21 ADC INPUT BLACK LEVEL ADJUST ........................................................................... 22 OVERALL SIGNAL FLOW SUMMARY ......................................................................... 23 CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT ...................................... 24 OUTPUT FORMATS ..................................................................................................... 25 PROGRAMMABLE AUTOMATIC BLACK LEVEL CALIBRATION ................................ 26 INDICATING THE START OF A BLC PROCEDURE .................................................... 27 BLC DURATION CONTROL ......................................................................................... 28 BLC WORKED EXAMPLE: ............................................................................................ 29 BLC SCENARIOS OF OPERATION.............................................................................. 31 REFERENCES .............................................................................................................. 35 POWER MANAGEMENT .............................................................................................. 35 CONTROL INTERFACE ................................................................................................ 35 MULTIPLE DEVICE OPERATION ................................................................................. 36 OPERATING MODES ................................................................................................... 39 16-BIT MODE ................................................................................................................ 39 10-BIT MODE ................................................................................................................ 40 DEVICE CONFIGURATION ................................................................................. 41 REGISTER MAP ............................................................................................................ 41 REGISTER MAP DESCRIPTION .................................................................................. 42 APPLICATIONS INFORMATION ........................................................................ 47 RECOMMENDED EXTERNAL COMPONENTS ........................................................... 47 RECOMMENDED EXTERNAL COMPONENT VALUES .............................................. 47 PACKAGE DIMENSIONS .................................................................................... 48 PD, Rev 4.2, September 2013 w 2