WM8753L w Hi-Fi and Telephony Dual CODEC DESCRIPTION FEATURES 2 The WM8753L is a low power, high quality stereo CODEC Hi-fi DAC: interfaced over I S type link with integrated Voice CODEC designed for portable digital Audio sample rates: telephony applications such as mobile phone, or headset 8, 11.025, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96 with hi-fi playback capability. DAC SNR 98dB, THD -84dB (A weighted 48kHz) ADC SNR 95dB, THD -82dB (A weighted 48kHz) The device integrates dual interfaces to two differentially On-chip Headphone Driver with cap-less output option connected microphones, and includes drivers for speakers, - 40mW output power on 16 / 3.3V headphone and earpiece. External component requirements - with 16 load: SNR 90dB, THD 75dB are reduced as no separate microphone or headphone - with 10k load: SNR 94dB, THD 90dB amplifiers are required, and Cap-less connections can be On-chip speaker driver with 0.5W into 8R made to all loads. Advanced on-chip digital signal Voice CODEC: interfaced over Voice interface processing performs tone control, Bass Boost and automatic supports sample rates from 8ks/s to 48ks/s level control for the microphone or line input through the ADC and DAC SNR 82dB, THD -74dB ADC. The two ADCs may be used to support Voice noise Two Differential Microphone Interfaces cancellation in a partnering DSP, or for stereo recording. - Dual ADCs support noise cancellation in external DSP The WM8753L hi-fi DAC can operate as a master or a slave, - Programmable ALC / Noise Gate with various master clock frequencies including 12 or Low-noise bias supplied for electret microphones 24MHz for USB devices, 13MHz or 19.2MHz for cellular Other Features systems, or standard 256fs rates like 12.288MHz and On-chip PLLs supporting 12, 13, 19.2MHz and other clocks 24.576MHz. Internal PLLs generate all required clocks for Cap-less connection options to headphones, earpiece, spkr. both Voice and hi-fi converters. If audio system clocks Low power, low voltage already exist, the PLLs may be committed to alternative - 1.8V to 3.6V (digital core: 1.42V to 3.6V) uses. - power consumption <20mW all-on with 2V supplies - <12mW for PCM CODEC operation The WM8753L operates at a nominal supply voltage of 2V, 7x7x0.9mm QFN package although the digital core can operate at voltages down to 1.42V to save power, and the maximum for all supplies is APPLICATIONS 3.6 Volts. Different sections of the chip can also be powered down under software control. MP3 Player / Recorder mobile phone Bluetooth stereo headset WOLFSON MICROELECTRONICS plc Production Data, November 2011, Rev 4.2 To receive regular email updates, sign up at Production Data WM8753L TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS .................................................................................................... 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION - QFN ............................................................................... 4 ORDERING INFORMATION .................................................................................. 4 PIN DESCRIPTION ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ........................................................................ 6 SIMULATED THERMAL PROPERTIES ........................................................................... 6 RECOMMENDED OPERATING CONDITIONS ..................................................... 6 ELECTRICAL CHARACTERISTICS ..................................................................... 7 TERMINOLOGY ................................................................................................................ 9 OUTPUT PGAS LINEARITY .......................................................................................... 10 POWER CONSUMPTION .................................................................................... 11 SIGNAL TIMING REQUIREMENTS .................................................................... 12 SYSTEM CLOCK TIMING ............................................................................................... 12 MODE/GPIO3 AND CSB/GPIO5 LATCH ON POWERUP TIMING ............................... 12 AUDIO INTERFACE TIMING MASTER MODE ........................................................... 13 AUDIO INTERFACE TIMING SLAVE MODE .............................................................. 14 CONTROL INTERFACE TIMING 3-WIRE MODE ....................................................... 15 CONTROL INTERFACE TIMING 2-WIRE MODE ....................................................... 16 INTERNAL POWER ON RESET CIRCUIT .......................................................... 17 DEVICE DESCRIPTION ...................................................................................... 18 INTRODUCTION ............................................................................................................. 18 INPUT SIGNAL PATH ..................................................................................................... 20 MICROPHONE INPUTS ................................................................................................. 24 PGA CONTROL ............................................................................................................... 28 AUTOMATIC LEVEL CONTROL (ALC) .......................................................................... 31 3D STEREO ENHANCEMENT ....................................................................................... 34 OUTPUT SIGNAL PATH ................................................................................................. 36 ANALOGUE OUTPUTS ................................................................................................... 42 HEADPHONE SWITCH ................................................................................................... 46 HEADPHONE OUTPUT .................................................................................................. 47 INTERRUPT CONTROLLER .......................................................................................... 48 GENERAL PURPOSE INPUT/OUTPUT ......................................................................... 51 DIGITAL AUDIO INTERFACES ...................................................................................... 53 AUDIO INTERFACES CONTROL ................................................................................... 58 CONTROL INTERFACE .................................................................................................. 62 MASTER CLOCK AND PHASE LOCKED LOOP ........................................................... 66 AUDIO SAMPLE RATES ................................................................................................. 69 POWER SUPPLIES ......................................................................................................... 71 POWER MANAGEMENT ................................................................................................ 72 REGISTER MAP .............................................................................................................. 77 DIGITAL FILTER CHARACTERISTICS .............................................................. 79 TERMINOLOGY .............................................................................................................. 80 DAC FILTER RESPONSES ............................................................................................ 81 ADC FILTER RESPONSES ............................................................................................ 82 VOICE FILTER RESPONSES ............................................................................. 84 VOICE DAC FILTER RESPONSES ................................................................................ 84 VOICE ADC FILTER RESPONSES ................................................................................ 84 PD, Rev 4.2, November 2011 w 2