WM8805GEDS/V

WM8805 w 8:1 Digital Interface Transceiver with PLL DESCRIPTION FEATURES S/PDIF (IEC60958-3) compliant. The WM8805 is a high performance consumer mode S/PDIF transceiver with support for 8 received Channels Advanced jitter attenuating PLL with low intrinsic period and 1 transmitted Channel. jitter of 50 ps RMS. S/PDIF recovered clock using PLL, or stand alone crystal A crystal derived, or externally provided high quality master derived clock generation. clock is used to allow low jitter recovery of S/PDIF supplied Supports 10 27MHz crystal clock frequencies. master clocks. 2-wire / 3-Wire serial or hardware control interface. Generation of all typically used audio clocks is possible Programmable Audio data interface modes: using the high performance internal PLL. A dedicated 2 - I S, Left, Right Justified or DSP CLKOUT pin provides a high drive clock output. - 16/20/24 bit word lengths A pass through option is provided which allows the device 8 channel receiver input and 1 channel transmit output. simply to be used to clean up (de-jitter) the received digital Auto frequency detection / synchronisation. audio signals. Selectable output status data bits. The device may be used under software control or stand Up to 8 configurable GPO pins. alone hardware control modes. In software control mode, De-emphasis flag output. both 2-wire with read back and 3-wire interface modes are TM TM supported. Non-audio detection including DOLBY and DTS . Channel status changed flag. Status and error monitoring is built-in and results can be Configurable clock distribution with selectable output read back over the control interface, on the GPO pins or MCLK rate of 512fs, 256fs, 128fs and 64fs. streamed over the audio data interface in With Flags mode (audio data with status flags appended). 2.7 to 3.6V digital and PLL supply voltages. 2 28-lead SSOP package. The audio data interface supports I S, left justified, right justified and DSP audio formats of 16-24 bit word length, APPLICATIONS with sample rates from 32 to 192ks/s. Surround Sound AV processors and Hi-Fi systems The device is supplied in a 28-lead Pb-free SSOP package. Music industry applications DVD-P/DVD-RW Digital TV BLOCK DIAGRAM WOLFSON MICROELECTRONICS plc Production Data, March 09, Rev 4.5 To receive regular email updates, sign up at WM8805 Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 BLOCK DIAGRAM ................................................................................................. 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION ........................................................................................... 3 ORDERING INFORMATION .................................................................................. 3 PIN DESCRIPTION ................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ......................................................................... 5 RECOMMENDED OPERATING CONDITIONS ..................................................... 6 SUPPLY CURRENT ...................................................................................................... 6 ELECTRICAL CHARACTERISTICS ...................................................................... 6 MASTER CLOCK TIMING...................................................................................... 7 DIGITAL AUDIO INTERFACE MASTER MODE ......................................................... 7 DIGITAL AUDIO INTERFACE SLAVE MODE ............................................................ 8 CONTROL INTERFACE 3-WIRE MODE .................................................................... 9 CONTROL INTERFACE 2-WIRE MODE .................................................................. 10 DEVICE DESCRIPTION ....................................................................................... 11 INTRODUCTION ......................................................................................................... 11 POWER UP CONFIGURATION .................................................................................. 12 HARDWARE CONTROL MODE .................................................................................. 18 DIGITAL ROUTING CONTROL ................................................................................... 20 MASTER CLOCK AND PHASE LOCKED LOOP ......................................................... 21 SOFTWARE MODE INTERNAL CLOCKING .............................................................. 21 HARDWARE MODE INTERNAL CLOCKING .............................................................. 30 S/PDIF TRANSMITTER ............................................................................................... 31 S/PDIF RECEIVER ...................................................................................................... 34 GENERAL PURPOSE OUTPUT (GPO) CONFIGURATION ....................................... 44 DIGITAL AUDIO INTERFACE ..................................................................................... 45 AUDIO DATA FORMATS ............................................................................................ 46 REGISTER MAP ......................................................................................................... 53 APPLICATIONS INFORMATION ......................................................................... 64 RECOMMENDED EXTERNAL COMPONENTS .......................................................... 64 PACKAGE DIMENSIONS .................................................................................... 65 IMPORTANT NOTICE .......................................................................................... 66 ADDRESS: .................................................................................................................. 66 PD, Rev 4.5, March 2009 w 2