ST72324Bxx 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI Features Memories 8 to 32 Kbyte dual voltage High Density Flash LQFP44 LQFP32 (HDFlash) or ROM with readout protection 10 x 10 7 x 7 capability. In-application programming and In- circuit programming for HDFlash devices 384 bytes to 1 Kbyte RAM HDFlash endurance: 1 kcycle at 55 C, data SDIP42 SDIP32 retention 40 years at 85 C 600 mil 400 mil Clock, reset and supply management 4 timers Enhanced low voltage supervisor (LVD) with Main clock controller with real-time base, Beep programmable reset thresholds and auxiliary and clock-out capabilities voltage detector (AVD) with interrupt capability Configurable watchdog timer Clock sources: crystal/ceramic resonator 16-bit Timer A with 1 input capture, 1 output oscillators, int. RC osc. and ext. clock input compare, ext. clock input, PWM and pulse PLL for 2x frequency multiplication generator modes 4 power saving modes: Slow, Wait, Active-halt, 16-bit Timer B with 2 input captures, 2 output and Halt compares, PWM and pulse generator modes Interrupt management 2 communication interfaces Nested interrupt controller. 10 interrupt vectors SPI synchronous serial interface plus TRAP and RESET. 9/6 ext. interrupt lines SCI asynchronous serial interface (on 4 vectors) 1 analog peripheral (low current coupling) Up to 32 I/O ports 10-bit ADC with up to 12 input ports 32/24 multifunctional bidirectional I/Os, 22/17 alternate function lines, Development tools 12/10 high sink outputs In-circuit testing capability Table 1. Device summary Device Memory RAM (stack) Voltage range Temp. range Package ST72324BK2 Flash/ROM 8 Kbytes 384 (256) bytes LQFP32 ST72324BK4 Flash/ROM 16 Kbytes 512 (256) bytes 7x7/ SDIP32 ST72324BK6 Flash/ROM 32 Kbytes 1024 (256) bytes up to 3.8 to 5.5 V -40 to 125 C ST72324BJ2 Flash/ROM 8 Kbytes 384 (256) bytes LQFP44 ST72324BJ4 Flash/ROM 16 Kbytes 512 (256) bytes 10x10/ SDIP42 ST72324BJ6 Flash/ROM 32 Kbytes 1024 (256) bytes March 2009 Rev 7 1/193 www.st.com 1Contents ST72324Bxx Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.7.1 Flash Control/Status Register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.4 Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.5 Stack Pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 PLL (phase locked loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.1 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.2 Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2/193