80-000492 Critical Link

MityCAM Solutions Vision Development Kit FEATURES APPLICATIONS High Performance MityDSP-L138F Machine Vision CPU Quality Control - TI OMAP-L138 Semiconductor Inspection - Xilinx Spartan 6 FPGA Image Processing (DSP and FPGA) Vision Sensor Boards Supported - 0.3MP Monochrome - 0.3MP Color Digital Interfaces - 1.0MP Monochrome DVI Video Output - 5.0MP Monochrome 10/100 Mbit Ethernet Interface - 5.0MP Color Audio Output Video Capture USB Host and OTG Image Analysis CAN Bus Interface Linux and HMI (Qt) SD/MMC Card Socket Expansion Additional Hardware UART Header (RS232 or RS485) AC to DC 12V Adapter WQVGA LCD Interface Tripod for Camera 4 Status LEDs Pre-Loaded SD card 4-Pin GPIO Header Camera Lens Ethernet and Serial Cables Overview The Vision Development Kit (VDK) by Critical Link is a complete hardware and software framework designed to accelerate the development of vision applications. The framework offers both a Xilinx Spartan 6 FPGA and a TI OMAP-L138 dual core processor, and is based on Critical Links production-ready MityDSP-L138F System on Module (SoM). Figure 1 - Vision Development Kit 1 Critical Link, LLC PHONE 315.425.4045 6712 Brooklawn Parkway FAX 315.425.4048 Sy Syracuse, NY 13211 www.CriticalLink.com MityCAM Solutions Vision Development Kit The system is designed to route raw video data from the CCD sensor board into the MityDSP-L138F. The FPGA captures the input data and performs optional user defined algorithm(s) on the video data, then routes the data to the DSP core of the OMAP-L138 processor via the UPP interface. The DSP can then performs additional processing and notifies the ARM core that the final processed video data (or results if no final video data is required) is available via a DSPLINK shared memory interface. The ARM accepts the data and updates the local frame buffer with the needed results using a Qt drawing framework. Figure 2 shows a system block diagram for the Xilinx FPGA and DSP and ARM cores (TI OMAP-L138). Industrial I/O Board with Industrial Camera Expansion Board MITYDSP-L138F Spartan 6 LX16 OMAP-L138 FPGA 674X+ CORE ALGOR 1 ALGOR 1 DATA UPP UPP APTINA Scatter / ALGOR 2 J 16 SENSOR ALGOR 2 FIFO Gather 7 ASYNC J5 DMA 0 LV FIFO engine 0 CLK ALGOR 3 ALGOR 3 ALGOR N ALGOR N DVI TFP710 EMIFA Control Logic Control Logic Results DSPLINK Qt Control Application LCDC Compile CTLR Time Linux J LCD 1 Routing Frame Buffer Logic 0 4 OMAP-L138 ARM 9 Core Figure 2 System Block Diagram for FPGA, DSP, and ARM This document covers the following topics: Major system components: Sensor, FPGA, DSP, and ARM Hardware Design Information Key interfaces Development tools Getting started Examples Included Components and Ordering information 2 Critical Link, LLC PHONE 315.425.4045 6712 Brooklawn Parkway FAX 315.425.4048 Sy Syracuse, NY 13211 www.CriticalLink.com HS