SATA3 Host CPUless IP Core April 10, 2020 Product Specification Rev1.0 Core Facts Provided with Core Design Gateway Co.,Ltd Documentation Reference Design Manual th 54 BB Building 14 Fl., Room No.1402 Sukhumvit Demo Instruction Manual 21 Rd. (Asoke), Klongtoey-Nua, Wattana, Design File Formats Encrypted Netlist File Bangkok 10110 Instantiation Templates VHDL Phone: 66(0)2-261-2277 Reference Designs & Vivado Project, Fax: 66(0)2-261-2290 Application Notes See Reference Design Manual E-mail: ip-sales design-gateway.com Additional Items URL: www.design-gateway.com Demo on ZC706/KCU105/ZCU102/VCU118 Support Features Support Provided by Design Gateway Co., Ltd. Simple user interface by dgIF typeS Support four commands, i.e. IDENTIFY DEVICE, SECURITY ERASE UNIT, WRITE DMA (EXT), and READ DMA (EXT) SATA application layer, transaction layer and link layer by hardware logic No need for external memory and CPU Compliant with the Serial ATA specification revision 3.0 2 x 4Kbyte FIFO for internal buffer Support SATA-III Speed by using 150 MHz for SATA clock and higher frequency for User clock Free HDL code of SATA3 PHY and the reference design in release stuff Reference design by using AB12-HSMCRAID or AB09-FMCRAID adapter board from Design Gateway Table 1: Example Implementation Statistics for Ultrascale device Fmax CLB CLB Design 1 CLB PLL Family Example Device IOB BUFG BRAMTile GTH/GTY (MHz) Regs LUTs Tools Kintex-Ultrascale XCKU040FFVA1156-2E 370 1474 1488 316 - - 1 - 1 Vivado2017.4 Zynq-Ultrascale+ XCZU9EG-FFVB1156-2-I >500 1475 1592 328 - - 1 - 1 Vivado2017.4 Virtex-Ultrascale+ XCVU9P-FLGA2104-2L-E >500 1474 1597 318 - - 1 - 1 Vivado2017.4 Table 2: Example Implementation Statistics for 7-Series device Fmax Slice Slice Design 1 Slices PLL Family Example Device IOB BUFG BRAMTile GTP/GTX (MHz) Regs LUTs Tools Zynq-7000 XC7Z045FFG900-2 333 1474 1500 563 - - 1 - 1 Vivado2017.4 Notes: 1) Actual resouce dependent on percentage of unrelated logic. 2) Transceiver is not used in the IP core, but used in SATA PHY design April 10, 2020 SATA3 Host CPUless IP Core Figure 1: SATA3 Host CPUless IP Block Diagram Applications SATA3 Host CPUless IP Core (SATA3H-CL IP) is ideal to access SATA device without using both CPU and external memory. User interface of the IP is dgIF typeS which is easy to use. The resource utilization of the IP is less, but it can achieve very high performance. Using multiple IPs for RAID0 can increase total performance of storage system. So, it is recommended to use the IP in high-speed data recording system or big-data storage. 2 April 10, 2020