PI6C48535-11B 3.3V Low Jitter 1-to-4 Crystal/LVCMOS to LVPECL Fanout Buffer Features Description Maximum output frequency: 500MHz The PI6C48535-11B is a high-performance low jitter and low-skew 4 pair of differential LVPECL outputs LVPECL fanout buffer. PI6C48535-11B features selectable of single-ended clock or crystal inputs and translates to four LVPECL Selectable CLK and crystal inputs outputs. The CLK input accepts LVCMOS or LVTTL signals. The CLK accepts LVCMOS, LVTTL input level outputs are synchronized with input clock during asynchronous as- Ultra low additive phase jitter: < 0.05 ps (typ) (differential sertion /deassertion of CLK EN pin. PI6C48535-11B is ideal for 156.25MHz, 12KHz to 20MHz integration range) crystal or LVCMOS/LVTTL to LVPECL translation. Typical clock Output Skew: 30ps (maximum) translation and distribution applications are data-communications Part-to-part skew: 200ps (maximum) and telecommunications. Propagation delay: 1.5ns (maximum) 3.3V power supply Pin-to-pin compatible to ICS8535-11, ICS8535-31 o o Operating Temperature: -40 C to 85 C Packaging (Pb-free & Green available): - 20-pin TSSOP (L) Block Diagram Pin Diagram CLK EN D V 1 EE 20 Q 0 Q CLK EN 2 19 Q N 0 CLK SEL 3 18 V LE DD CLK 4 17 Q 1 NC 5 16 Q N 1 CLK 0 Q 0 Xtal 1 6 15 Q 2 Q n 0 Xtal 2 7 14 Q Xtal1 N 2 1 Xtal2 NC 8 13 V DD Q 1 NC 9 12 Q 3 Q n 1 V DD 10 11 Q N 3 Q 2 CLK SEL Q n 2 Q 3 Q n 3 www.pericom.com PI6C48535-11B Rev A 06/01/12 1 12-0203PI6C48535-11B 3.3V Low Jitter 1-to-4 Crystal/LVCMOS to LVPECL Fanout Buffer Pin Description Name Pin Type Description V 1 P Connect to Negative power supply EE Synchronizing clock enable. When high, clock outputs follow clock input. When low, Q x CLK EN 2 I PU outputs are forced low, Q outputs are forced high. LVCMOS/LVTTL level with 50K n x pull up. Clock select input. When high, selects Xtal (Xtal1, Xtal2) inputs. When low, selects CLK CLK SEL 3 I PD input. LVCMOS/LVTTL level with 50K pull down. CLK 4 I PD LVCMOS / LVTTL clock input Xtal1, 6, 7 Crystal input and output Xtal2 NC 5, 8, 9 No internal connection. 10, 13, V P Connect to 3.3V DD 18 Q , Q 11, 12 O Differential output pair, LVPECL interface level. 3 n 3 Q , nQ2 14, 15 O Differential output pair, LVPECL interface level. 2 Q , Q 16, 17 O Differential output pair, LVPECL interface level. 1 n 1 Q , Q 19, 20 O Differential output pair, LVPECL interface level. 0 n 0 Notes: 1. I = Input, O = Output, P = Power supply connection, I PD = Input with pull down, I PU = Input with pull up Pin Characteristics Symbol Parameter Conditions Min. Typ. Max. Units C Input Capacitance 4 pF IN R pullup Input Pullup Resistance 50 K R pulldown Input Pulldown Resistance 50 K Control Input Function Table Inputs Outputs CLK EN CLK SEL Selected Source Q :Q Q : Q 0 3 n 0 n 3 0 0 CLK Diasbled: Low Diasbled: High 0 1 Xtal1, Xtal2 Disabled: Low Disabled: High 1 0 CLK Enabled Enabled 1 1 Xtal1, Xtal2 Enabled Enabled Notes: 1. After CLK EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below. www.pericom.com PI6C48535-11B Rev A 06/01/12 2 12-0203