PI6C4911510-05 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with Sync OE Features Description F < 1.5GHz e PTh I6C4911510-05 is a high-performance low-skew 1-to-10 LVPE - MAX CL/ ECL fanout buffer. The PI6C4911510-05 features two selectable 10 pairs of differential LVPECL/ ECL outputs differentia l clock inputs and translates to ten LVPECL/ ECL outputs. Low additive jitter, < 0.03ps (typ) e CTh LK inputs accept LVPECL, LVDS, CML and SSTL signals. Selectable differential input pairs with single ended input PI6C4911510-05 is ideal for clock distribution applications such option as providing fanout for low noise Pericom oscillators. Input CLK accepts: LVPECL, LVDS, CML, SSTL input level Output skew: 55ps (max) o o Operating Temperature: -40 C to 85 C ECL mode operating voltage range V / V = 0V, V = -3.6V to -2.375V DD DDO EE Power supply: 3.3V 10% or 2.5V 5% Packaging (Pb-free & Green), 32-pin TQFP available Block Diagram Pin Configuration Q0+ Q0- Q1+ Q1- Q2+ Q2- 24 VDD 1 Q3+ Q3+ 23 CLK SEL 2 Q3- Q3- CLK0 0 Q4+ 22 nCLK0 CLK0 3 Q4+ Q4- CLK1 1 21 nCLK0 4 Q4- nCLK1 Q5+ 20 SYNC OE 5 Q5+ Q5- 19 Q6+ CLK1 6 Q5- CLK SEL Q6- 18 nCLK1 7 Q6+ Q7+ SYNC OE D 17 VEE 8 Q6- Q Q7- Q8+ LE Q8- Q9+ Q9- PI6C4911510-05 Rev C 10/09/2013 1 13-0151 9 VDDO 32 VDDO Q9- 10 31 Q0+ 11 30 Q9+ Q0- 12 Q8- 29 Q1+ Q8+ 13 28 Q1- 14 27 Q7- Q2+ 15 Q7+ 26 Q2- VDDO 16 25 VDDOPI6C4911510-05 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer w/ Sync OE Pin Description Pin Name Type Description 1 V Power Core Power Supply DD Clock select input. When high, selects CLK1 input. When low, selects CLK0 input. 2 CLK SEL Input LVCMOS/LVTTL level with 50k pull down. 3 CLK0 Input Differential clock input with pull-down 4 nCLK0 Input Inverting differential clock input. Defaults to V /2 if left floating. DD Synchronizing clock enable. When HIGH, clock outputs follow clock input. 5 SYNC OE Input When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. 6 CLK1 Input Differential clock input with pull-down 7 nCLK1 Input Inverting differential clock input. Defaults to V /2 if left floating. DD 8 V Power Connect to negative power supply EE 9, 16, 25, 32 V Power Output Power pin DDO 11, 10 Q9+, Q9- Output Differential output pair, LVPECL interface level. 13,12 Q8+, Q8- Output Differential output pair, LVPECL interface level. 15,14 Q7+, Q7- Output Differential output pair, LVPECL interface level. 18,17 Q6+, Q6- Output Differential output pair, LVPECL interface level. 20,19 Q5+, Q5- Output Differential output pair, LVPECL interface level. 22,21 Q4+, Q4- Output Differential output pair, LVPECL interface level. 24, 23 Q3+, Q3- Output Differential output pair, LVPECL interface level. 27,26 Q2+, Q2- Output Differential output pair, LVPECL interface level. 29,28 Q1+, Q1- Output Differential output pair, LVPECL interface level. 31,30 Q0+, Q0- Output Differential output pair, LVPECL interface level. CLK SEL Input Function Table Inputs Outputs 0 CLK0 1 CLK1 2 PI6C4911510-05 Rev C 10/09/2013 13-0151