A product Line of Pb Diodes Incorporated Lead-free Green PI6CB33402 Very Low Power 4-Output PCIe Clock Buffer With On-Chip Termination Features Description 3.3V supply voltage e PTh I6CB33402 is a 4-output very low power PCIe Gen1/Gen2/ Gen3/Gen4/Gen5 clock buffer. It takes a reference input to fanout HCSL input: 100MHz, also support 50MHz, 125MHz or four 100MHz low power differential HCSL outputs with on-chip 133.33MHz via SMBus terminations. The on-chip termination can save 16 external resis - 4 differential low power HCSL outputs with on-chip tors and make layout easier. Individual OE pin for each output termination provides easier power management. Default Z = 85 OUT Spread spectrum tolerant It uses Diodes proprietary PLL design to achieve very low jitter that meets PCIe Gen1/Gen2/Gen3/Gen4/Gen5 requirements. Individual output enable Other than PCIe 100MHz support, this device also support Eth- Programmable Slew rate and output amplitude for each output ernet application with 50MHz, 125MHz and 133.33MHz via Differential outputs blocked until PLL is locked SMBus. It provides various options such as different slew rate and Strapping pins or SMBus for configuration amplitude through SMBUS so that users can configure the de - vice easily to get the optimized performance for their individual Differential output-to-output skew <50ps boards. Very low jitter outputs Differential cycle-to-cycle jitter <50ps PCIe Gen1/Gen2/Gen3/Gen4/Gen5 CC compliant Block Diagram PCIe Gen 2 and 3 SRiS and SRnS compliant OE 3:0 Q3 Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. Green Device (Note 3) Q2 IN+ PLL For automotive applications requiring specic cfi hange control IN- Q1 (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please Q0 contact us or your local Diodes representative. SCLK SDATA A product Line of Diodes Incorporated PI6CB33402 Pin Configuration OE 3:0 Q3 Q2 32 31 30 29 28 27 26 25 IN+ PLL BW SEL TRI 1 24 OE2 IN- Q1 NC 2 23 Q2- NC 3 22 Q2+ Q0 V SCLK 4 21 DD R VDDA SDATA GND IN+ 5 20 NC SADR TRI CTRL BW SEL TRI LOGIC OE1 6 19 IN- PD Q1- NC 7 18 Q1+ GND DIG 8 17 9 10 11 12 13 14 15 16 Pin Description Pin Number Pin Name Type Description Latch to select low loop bandwidth, bypass PLL, and high loop band- 1 BW SEL TRI Input Tri-level width. This pin has both internal pull-up and pull-down 2 NC Internal connected for feedback loop. Do not connect this pin 3 NC Internal connected for feedback loop. Do not connect this pin 4 V R Power Power supply for input differential buffers DD 5 IN+ Input Differential true clock input 6 IN- Input Differential complementary clock input 7 NC Do not connect this pin 8 GND DIG Power Ground for digital circuitry 9 SCLK Input CMOS SMBUS clock input, 3.3V tolerant Input/ 10 SDATA CMOS SMBUS Data line, 3.3V tolerant Output 11 V DIG Power Power supply for digital circuitry, nominal 3.3V DD Active low input for enabling Q0 pair. This pin has an internal pull-down. 12 OE0 Input CMOS 1 =disable outputs, 0 = enable outputs 13 Q0+ Output HCSL Differential true clock output 14 Q0- Output HCSL Differential complementary clock output 15, 25 V Power Power supply for differential outputs DDO 16 NC Do not connect this pin 17 Q1+ Output HCSL Differential true clock output 18 Q1- Output HCSL Differential complementary clock output www.diodes.com January 2020 PI6CB33402 22 Diodes Incorporated Document Number DS41293 Rev 5-2 SCLK SADR TRI SDATA PD V DIG NC DD OE3 OE0 Q0+ Q3- Q3+ Q0- V O NC DD V O DD NC