REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add CAGE number 50364 as a supplier for 02 and 03 device types. 89-08-23 M. A. Frye Add 04 device type. Add CAGE number 1FN41 as a supplier of the K package. Editorial changes throughout entire document. Remove C as a test condition option. B Change C and C values in Table I. Incorporate power reset feature. 91-11-06 M. A. Frye I O Add 05 device. Add CAGE number 65786 for 04K, 04L and 043 devices. Add footnote 7/ to Table I. Editorial changes throughout entire document. C Update drawing to current requirements. Editorial changes 01-11-02 Raymond Monnin throughout. - gap D Boilerplate update part of 5 year review. ksr 06-08-18 Raymond Monnin E 10-03-29 Charles F. Saffle Corrected I and I parameters in Table I. ksr IL IH THE ORIGINAL FRONT PAGE HAS BEEN REPLACED. REV SHEET REV SHEET REV STATUS REV E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Jeffery D. Bowling DEFENSE SUPPLY CENTER COLUMBUS CHECKED BY COLUMBUS, OHIO 43218-3990 STANDARD 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88670 01 L X Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 C22V10 22-input 10-output 25 ns and-or-logic array 02 C22V10 22-input 10-output 30 ns and-or-logic array 03 C22V10 22-input 10-output 40 ns and-or-logic array 04 C22V10 22-input 10-output 20 ns and-or-logic array 05 C22V10 22-input 10-output 15 ns and-or-logic array 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 Flat package L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 3 CQCC1-N28 28 Leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range ........................................................................ -0.5 V dc to +7.0 V dc Input voltage range .......................................................................... -2.0 V dc to +7.0 V dc 2/ Output voltage applied range ........................................................... -0.5 V dc to +7.0 V dc 2/ Output sink current ........................................................................... 16 mA Thermal resistance, junction-to-case ( ): ...................................... See MIL-STD-1835 JC Maximum power dissipation (P ) 3/ ................................................. 1.2 W D Maximum junction temperature (T ) ................................................. +175C J Lead temperature (soldering, 10 seconds maximum) ...................... +260C Storage temperature range .............................................................. -65C to +150C Temperature under bias ................................................................... -55C to +125C 1/ All voltages referenced to V . SS 2/ Minimum voltage is -0.6 V dc which may undershoot to -2.0 V dc for pulses of less than 20 ns. Maximum output pin voltage is V +0.75 V dc which may overshoot to +7.0 V dc for pulses of less than 20 ns. CC 3/ Must withstand the added P due to short circuit test e.g., I . D OS SIZE STANDARD 5962-88670 A MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS REVISION LEVEL SHEET COLUMBUS, OHIO 43218-3990 E 2 DSCC FORM 2234 APR 97