PC107A PCI Bridge Memory Controller Datasheet Features Processor Bus Frequency up to 100 MHz 64- or 32-bit Data Bus and 32-bit Address Bus Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible IEEE 1149.1 Compliant, JTAG Boundary-scan Interface PD Max = 1W (66 MHz), Full Operating Conditions Nap, Doze and Sleep Modes for Power Savings Two-channel Integrated DMA Controller Message Unit Intelligent Input/Output (Two-wire Interface) Message Controller Two Door Bell Registers Inbound and Outbound Messaging Registers Inter-integrated Circuit (Two-wire Interface) Controller, Full Master/Slave Support Embedded Programmable Interrupt Controller (EPIC) Five Hardware Interrupts (IRQs) or 16 Serial Interrupts Four Programmable Timers Description The PC107A PCI Bridge/Integrated Memory Controller provides a bridge between the Peripheral Component Interconnect, (PCI) bus and PowerPC 603e, PowerPC 740, PowerPC 750 or PC7400 microprocessors. PCI support allows system designers to design systems quickly using peripherals already designed for PCI and other stan- dard interfaces available in the personal computer hardware environment. The PC107A provides many other necessities for embedded applications including a high-performance memory controller and dual processor support, 2-channel flexible DMA controller, an interrupt controller, an I O-ready message unit, an inter-integrated circuit controller (Two-wire Interface), 2 and low skew clock drivers. The PC107A contains an Embedded Programmable Interrupt Controller (EPIC) featuring five hardware interrupts (IRQs) as well as sixteen serial interrupts along with four timers. The PC107A uses an advanced, 2.5V HiP3 process technology and is fully compatible with TTL devices. Visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors SAS 2007 0842EHIREL04/07PC107A Screening This product is manufactured in full compliance with: HiTCE CBGA according to e2v standards PBGA upscreening based upon e2v standards Full military temperature range (Tj = -55C, +125C) Industrial temperature range (Tj = -40C, +110C) 1. General Description 1.1 Simplified Block Diagram The PC107A integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt controller/tim- ers, a message unit with an Intelligent Input/Output (I O) message controller, and an Inter-integrated 2 Circuit (two-wire interface) controller. The integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system. Figure 1-1 shows the major functional units within the PC107A. Note that this is a conceptual block dia- gram intended to show the basic features rather than an attempt to show how these features are physically implemented. Figure 1-1. PC107A Block Diagram Additional features: Programmable I/O PC107 with Watchpoint JTAG/COP Interface 60x Bus Interface (64- or 32-Bit Data Bus) Power Management Peripheral Logic Block Data Bus Data (64-Bit) (64- or 32-bit) Address Data Path with 8-bit Parity Message (32-Bit) ECC Controller or ECC Unit (with I2O) Central Memory/ROM/ Memory Control Port X Control/ Controller Unit Address DMA Controller Configuration Registers SDRAM SYNC IN I2C I2C SDRAM Clocks Controller PCI Bus DLL CPU Clocks Interface Unit PCI SYNC IN PLL EPIC 5 IRQs/ Address PCI Interrupt 16 Serial Fanout Translator Arbiter Controller PCI Bus Clocks Interrupts Buffers /Timers 32-Bit Five OSC IN PCI Interface Request/Grant Pairs 2 0842EHIREL04/07 e2v semiconductors SAS 2007