DKXC5VADAPT-1

Product Flyer DKXC5VADAPT-1 October 2009 Version 1.0 DAC DK FPGA Adaptor FME/MS/DAC80/FL1/5630 Features Description The DKXC5VADAPT-1 DAC DK adaptor DAC development kit input data adaptor provides a quick and effective way to For DK86064-2 or DK86065-2 demonstrate a high speed data interface to the Provides direct connection to HiTech Fujitsu DK86064 and DK86065 high performance Global FPGA platform DAC development kits. The adaptor directly connects the DKs to the HiTech Global V5- When combined with HiTech Global FPGA PCIE2 FPGA platform. The HiTech Global FPGA development platform: board uses the Xilinx Virtex-5 device. LVDS data interface for one (065) or Additional headers support data input and output two (064) DAC cores to the FPGA, as well as power and control data Loop Clock system for optimum timing for the DAC. GPIO to FPGA Support for single supply operation Trademarks and registered trademarks are the property of their respective owners. DKXC5VADAPT-1 FPGA Board Adaptor 2004-2009 Fujitsu Microelectronics Europe GmbH Production Page 1 of 4 Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU MICROELECTRONICS sales representatives before ordering. The information and circuit diagrams in this document are presented as is, no license is granted by implication or otherwise. October 2009 Version 1.0 FME/MS/DAC80/FL1/5630 DKXC5VADAPT-1 DAC DK FPGA Adaptor System Overview The most popular device for interfacing to high-speed data converters is an FPGA. FPGAs provide a relatively low-cost platform for high-speed logic, data processing, digital data interfaces and clock management. The DKXC5VADAPT-1 adaptor demonstrates how simple it is to implement a high-performance interface between an FPGA and the Fujitsu DK8606x DAC DKs. The adaptor is designed to interface directly to the HiTech Global V5-PCIE2 FPGA prototype Complete system board to combine the power of the Xilinx Virtex-5 with the high-speed Fujitsu DAC. DAC Interface All data and clock lines between the DAC and System Setup FPGA are matched LVDS pairs. The adaptor The DKXC5VADAPT-1 provides a physical can be used with both the DK86064-2 and link between the data headers on the DK86065-2. DK86064/65-2 and the HiTech Global V5- PCIE2. The underside of the adaptor features Maintaining valid clock-to-data timing can 6 Samtec sockets that plug directly into the prove to be a difficult task when using high- speed data converters. The MB86064/65 headers on the two boards. DACs avoid potential problems through the provision of a Loop Clock system. The Loop Clock is generated in sync with the DAC data at the FPGA output. This clock is passed through a user programmable delay in the DAC and then routed back to the FPGAs PLL feedback input. Altering the delays in the divided clock or Loop Clock signals allows the user to advance or retard data timings in order to find the optimum data eye. Once calibrated, the system automatically compensates for the effects of device-to-device variations, voltage and temperature (PVT). DDAACC CClloocckk Adaptor underside view The board connects 28 LVDS data pairs, the GGCCLLKK DAC loop clock pairs and two divided clock CCLLKK OOUUTT RReettaarrdd CCLLKKIINN ddaattaa signals between the two boards. All clock CCLLKKFFBBIINN GGCCLLKK PPLLLL signals are routed to dedicated global clock LLPPCCLLKK OOUUTT inputs on the FPGA. CCLLKKOOUUTT AAddvvaannccee GGCCLLKK ddaattaa OOSSEERRDDEESS LLPPCCLLKK IINN The complete system forms a compact 1144 1144 1144 OOSSEERRDDEESS DDAACC OOSSEERRDDEESS DDAATTAA solution ideal for testing and developing an AA11--AA1144 FFuujjiittssuu DDAACC FFPPGGAA FPGA-DAC interface. Loop Clock block diagram Page 2 of 4 Production 2004-2009 Fujitsu Microelectronics Europe GmbH Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU MICROELECTRONICS sales representatives before ordering. The information and circuit diagrams in this document are presented as is, no license is granted by implication or otherwise.