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GLS55LD040M-133-I-BZJE

GLS55LD040M-133-I-BZJE electronic component of Greenliant

Datasheet
Memory Controllers PATA (ATA100) NAND Controller I-TEMP

Manufacturer: Greenliant
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5103: USD 20.2206 ea
Line Total: USD 103185.72

0 - Global Stock
MOQ: 5103  Multiples: 5103
Pack Size: 5103
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Ships to you between Tue. 28 May to Thu. 30 May

MOQ : 5103
Multiples : 5103
5103 : USD 17.3075

     
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GLS55LD040M PATA NAND Controller Fact Sheet 01.000 November 2011 Features Industry Standard PATA Bus Interface Pre-programmed Firmware - Host Interface: 16-bit access - Performs self-initialization on first system - Supports up to PIO Mode-4 Power-on - Supports up to Multi-Word DMA Mode-2 - Executes industry standard ATA/IDE commands - Supports up to Ultra DMA Mode-6 - Implements advanced wear-leveling algorithms to - Supports 48-bit Address Feature Set substantially increase the longevity of flash media Interface for Standard NAND Flash Media - Embedded Flash File System - Flash Media Interface: 8-bit per channel with 1, 2 Built-in Hardware ECC or 4 channel options - Corrects up to 12 random bits of error per 512- - Supports up to 16 flash media devices directly Byte sector up to 24 random bits of error per 1- - Supports up to 64 flash media devices with Kbyte sector external decoding logic Internal or External System Clock - Supports Single-Level Cell (SLC) or Multi-Level Multi-tasking Technology enables Fast Sustained Cell (MLC) flash media Read/Write Performance - Supports 4Kbyte and 8Kbyte program page size - MLC NAND - Two-plane operation - Up to 105 MByte/sec Read, 73 MByte/sec Write Low Power, 3.3V Host and NAND Flash Media (external clock) Interface - Up to 92 MByte/sec Read, 73 MByte/sec Write Low Power Operation (internal clock) - Active mode: 60mA (3.3V) (typical) - SLC NAND - Sleep mode: 800uA (3.3V) (typical) - Up to 109 MByte/sec Read/Write (external clock) Power Management Unit - Up to 92 MByte/sec Read, 109 MByte/sec Write (internal clock) - Immediate disabling of unused circuitry without Automatic Recognition and Initialization of Flash host intervention - Zero wake-up latency Media Devices Expanded Data Protection - Seamless integration into a standard SMT manufacturing process - Added data security through user-selectable Commercial and Industrial Temperature Range protection zones - 0C to 70C for commercial operation 20-Byte Unique ID for Enhanced Security - -40C to 85C for industrial operation - Factory Pre-programmed 10-Byte Unique ID - User-Programmable 10-Byte ID Package Programmable, Multi-tasking NAND Flash Media - 12mm x 12mm x 1.17mm (maximum height), 145-ball, 0.8mm ball pitch, TFBGA (BZJE) Interface All Devices are RoHS Compliant Firmware Storage in Embedded Flash Product Description The Greenliant PATA NAND Controller is the heart of a high- initial power-on, the PATA NAND Controller recognizes performance, flash media-based data storage system. The attached flash media devices, sets up a bad block table, NAND Controller recognizes the control, address and data executes all necessary handshaking routines for flash media signals on the ATA/IDE bus and translates them into support and performs the low level format. memory accesses to the standard NAND-type flash media. For added manufacturing flexibility, system debug, re- The GLS55LD040M device supports Single-Level Cell (SLC) initialization and user customization is accomplished through and Multi-Level Cell (MLC) flash media. This technology is the ATA/IDE interface. ideal for solid state mass storage applications offering For confidential information stored in the flash media, the expanded functionality, flexible capacity scaling capabilities GLS55LD040M provides exceptional security protection. and lower power consumption. Four password-protected protection zones can be set to The Greenliant PATA NAND Controller supports standard Read/Write, Read-only or Hidden (Read-disabled). The ATA/IDE protocols with up to PIO Mode-4, Multi-word DMA NAND Controller also provides a WP /PD pin to protect Mode-2, and Ultra DMA Mode-6 interface. It directly supports critical information stored in the flash media from up to 16 flash media devices or, through simple decoding unauthorized overwrites. logic, supports up to 64 flash media devices. The GLS55LD040M is available in an industry-standard, The PATA NAND Controller uses Embedded Flash memory 145-ball TFBGA package for easy integration into a surface and is factory pre-programmed with a flash file system. Upon mount technology manufacturing process. These specifications are subject to change without notice. 11/28/2011 2011 Greenliant Systems 1 S71408-F GLS55LD040M PATA NAND Controller Fact Sheet 01.000 November 2011 1.0 GENERAL DESCRIPTION The GLS55LD040M PATA NAND Controller contains a microcontroller and a flash file system integrated in a TFBGA package. Refer to Figure 2-1 for the PATA NAND Controller block diagram. The controller interfaces with the host system allowing data to be written to and read from the flash media. 1.1 Optimized PATA NAND Controller 5. Stores the data in Flash media upon completion The heart of the flash drive is the PATA NAND of a Write command. The PATA NAND Controller which translates standard ATA signals into Controller does not perform Post-Write flash media data and control signals. The following operations, except for when the Write cache is components contribute to the PATA NAND enabled by the Host command. Controllers operation. 1.1.6 Media Interface Block (MIB) 1.1.1 Microcontroller Unit (MCU) The GLS55LD040M contains two Media Interface The 32 bit RISC MCU transfers the ATA/IDE Blocks, MIB0 and MIB1. The MIB work independently commands into required flash media operations. to transfer data to and from the NAND Flash media. Each MIB controls two 8-bit channels. 1.1.2 Internal Direct Memory Access (DMA) Each Media Interface Block has three functions: DMA, The PATA NAND Controller uses internal DMA ECC and Programmable Multi-tasking NAND Interface. allowing instant data transfer from buffer to flash media. This implementation eliminates microcontroller 1.1.7 Programmable, Multi-tasking Interface overhead associated with the traditional, firmware- The multi-tasking interface enables fast, sustained based approach, thereby increasing the data transfer write performance by allowing multiple Read, Program, rate. and Erase operations to multiple flash media devices. 1.1.3 Power Management Unit (PMU) The ease with which the NAND interface can be programmed enables the quick support of new NAND The power management unit controls the power devices. consumption of the PATA NAND Controller. The PMU dramatically reduces the power consumption of the 1.1.8 Error Correction Code (ECC) PATA NAND Controller by putting the part of the The GLS55LD040M utilizes 24-bit, BCH Error circuitry that is not in operation into sleep mode. The detection Code (EDC) and Error Correction Code PMU is designed so that it has zero wake-up latency (ECC) algorithms. The ECC engine can provide, when using the internal clock. depending on settings, 6 or 12 bits of ECC for each 1.1.4 SRAM Buffer 512-Byte block of data, and 12 or 24 bits of ECC for A contributor to the PATA NAND Controller each 1KByte of data. performance is an SRAM buffer. The buffer optimizes The ECC encoding and decoding operations occur the Hosts data transfer from/to and to/from the flash during the data transfer. media. 1.1.9 Serial Communication Interface (SCI) 1.1.5 Embedded Flash File System The Serial Communication Interface (SCI) is designed The embedded flash file system is an integral part of to provide trace information during debugging the PATA NANDrive. It contains MCU firmware that processes. To aid in validation, always provide the performs the following tasks: SCI access to PCB design. 1. Translates host side signals into flash media writes and reads 1.1.10 External Clock 2. Provides advanced flash media wear leveling to The GLS55LD040M supports an external clock spread the flash writes to increase the longevity interface (XCLKI) that is enabled, or disabled, by the of flash media external clock enable (XCLKEN) input signal. With a 4.7K ohm pull-down resistor connected to the 3. Keeps track of data file structures XCLKEN pin, and a 6.0 MHz external oscillator or 4. Manages system security for the selected clock source present at the XCLKI input pin, the protection zones GLS55LD040M uses the external oscillator as the internal clock reference. These specifications are subject to change without notice. 11/28/2011 2011 Greenliant Systems 2 S71408-F

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

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