EV6R11 IX6R11 HALF BRIDGE DRIVER Evaluation Board Introduction Features The EV6R11 KIT implements a single power phase-leg Single chip for driving high/low side MOSFETs / TM circuit on a double-sided PCB, using the ISOSMART IGBTs HALF BRIDGE DRIVER CHIPSET - IX6R11and IXDP630 High to low side isolation of 600V dead time generator. This evaluation board includes an Common-mode dv/dt immunity of greater than assembled and tested PCB with two power devices. Just 50V/nanosecond follow the instructions in this document and connect the Undervoltage lockout board to the load and power. Optimized power circuit layout High side bootstrap supply Any power circuit is layout sensitive. The layout of this Sockets for freewheeling fast recovery diodes PCB is a proven, working layout. The designer is invited (FREDS) to duplicate this layout in his system, following the Flexibility of power level utilization evaluation of the driver chipset. 5V compatible HCMOS input logic with hysterisis Protection from cross conduction of the half Most systems vary in their power level requirements and bridge therefore the power devices used. Due to this fact and Simple, fast and low cost means of evaluation fluctuations in availability of power devices, the kit will not and design always include the same power devices. The designer is Option for using IXDP630 with RC oscillator or encouraged to use the power devices that are required for IXDP631 with crystal oscillator for improved dead his system. The devices that are enclosed serve only for time accuracy. initial evaluation. Three phase operation with the ability to attach additional slave driver boards. Figure 1: EV6R11 Assembled PCB With S3 Package Copyright IXYS CORPORATION 2003 First ReleaseR 6 10K R8 1K R7 1K R12 4.02K R11 4.02K R10 49.9 + EV6R11 KIT Schematic Diagram: P1 pins P1-1 GND P1-9 N/C P1-2 HIN P1-10 +VCL P1 P1-3 LIN P1-11 +VCL P1-4 Vdd supply lineP1-12 LS (VCL GND) P1-5 ENB active low P1-13 LS (VCL GND) P1-6 PWM IN P1-7 +5V for IXDB630 DC BUS P1-8 external 630 drive TESTPO INT C1 10UF 35V R9 D1 10 UF-1007DICT C8 C12 C7 + .1UF .1UF C2 2 D3 13 Q2 R2 ENB 8 1 IXF H7N 90Q .1UF HGO 5.11 3 U1 C13 U3 6 LM78L05AC Z HS .1UF + C10 C11 9 10UF 35V HS 2 .1UF GN D 1 Q2-S LGO TES TPO INT 12 HIN 2 LS C3 14 LI N .01UF C5 = 27 pF for IXDP630 16 LS C5 = 22 pF for IXDP631 C6 C5 22PF C4 27pF (22pF) C9 .1UF .1UF 1KV Y1 XM/SM 8 HGO 15 R3 ENB Q1-D TES TPO INT 1K / 1M U4 7 HS TP 5 1 TP 1 10 HS 2 TP 6 TP 2 1 1 14 R1 Q1 R HIN 2 1 IXF H7N90Q LGO 3 16 S LI N 5.11 3 13 TP3 TU 5 1 D2 T LS 12 JP1 TL 4 Q3 LS 2N 7000 2 15 1 3 18 ENAR SU LS ENAS U2 TP4 4 14 ENAS SL 1 IXD P630/631 Q4 R4 10K 6 2N7000 ENAT (Dead Timer) 17 1 3 RU LS GND JP2 16 RL TESTPOINT 7 OUTEN A ENAT R13 jumpered R14 open 8 RESET (ac tive low) R5 10K R15 jumpered R16 open Figure 3: EV6R11 PCB Schematic Schematic Notes: This is a demonstration PCB and has been designed for flexibility and ease of use. The schematic shows all options but does not mean the PCB is configured as such when ordered. The PCB will be loaded with either the IX6R11S3 16 pin SOIC package (U3) OR the IX6R11S6 18 pin SOIC package with heat sink tab (U4). The free-wheeling diodes, D2 and D3, are also not included but can be installed if IGBTs are used. Ordering: EV6R11S3 PCB with IX6R11S3 16 pin SOIC IC package EV6R11S6 PCB with IX6R11S6 18 pin SOIC IC package with heat tab 2 1 3 OU T IN 18 Vc c 1 1 2 2 9 10 3 GN D RCIN / XTLI N 3 4 4 5 5 11 6 OSC OU T 6 7 7 8 8 9 9 10 10 R3 = 1K for IXDP630 11 11 12 R3 = 1M for IXDP631 12 13 1 13 LOAD Y 1, C6 F OR IXD P631 1 1 2 2 17 DG 15 DG 11 Vdd 13 Vdd 5 N/ C 4 3 IX6R11S6 N/ C VC L IX6R11S3 6 3 N/ C VC L 5 N/ C 11 N/ C 9 10 VC H N/ C 12 7 N/ C VC H 10UF 35V 1 1 1 1