CY3125R62

5 CY3125 Warp CPLD Development Tool for UNIX Industry-standard PLDs (16V8, 20V8, 22V10) Features VHDL and Verilog timing model output for use with VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364) third-party simulators high-level language compilers with the following features: Static Timing Report: Designs are portable across multiple devices Provides timing information for any path broken and/or EDA environments down by the different steps of the path Facilitates the use of industry-standard simulation Architecture Explorer and Dynamic Timing Analysis for PSI, Delta39K and Quantum38K devices: and synthesis tools for board and system-level design Graphical representation of exactly how your design will be implemented on your specific target device Support for functions and libraries facilitating modular design methodology Zoom from the device level down to the macrocell level IEEE Standard 1076 and 1164 VHDL synthesis supports: Determine the timing for any path and view that path Enumerated types on a graphical representation of the chip Operator overloading Workstation support for Sun Solaris On-line documentation and help For... Generate statements Integers Functional Description IEEE Standard 1364 Verilog synthesis supports: Reduction and conditional operators Blocking and non-blocking procedural assignments VHDL Verilog State Machine While loops Integers Several design entry methods support high-level and low-level design descriptions: Behavioral VHDL and Verilog (IF...THEN...ELSE CASE...) Boolean TM UltraGen Structural Verilog and VHDL Synthesis and Designs can include multiple entry methods (but Fitting only one HDL language) in a single design. UltraGen Synthesis and Fitting Technology: Infers modules such as adders, comparators, etc., from behavioral descriptions and replaces them with circuits pre-optimized for the target device. User-selectable speed and/or area optimization on a block-by-block basis Perfect communication between synthesis and fit- VHDL, Verilog Programming Timing &Third-Party ting File Simulator Simulation Models Automatic selection of optimal flip-flop type (D type/T type) Figure 1. Warp VHDL Design Flow Automatic pin assignment Warp is a state-of-the-art HDL compiler for designing with Supports for the following Cypress Programmable Cypresss Complex Programmable Logic Devices (CPLDs). Logic Devices: Warp utilizes a subset of IEEE 1076/1164 VHDL and IEEE PSI (Programmable Serial Interface) 1364 Verilog as its Hardware Description Languages (HDL) for Delta39K CPLDs design entry. Then, it synthesizes and optimizes the entered design, and outputs a JEDEC or Intel hex file for the desired Quantum38K CPLDs PLD or CPLD (see Figure 1). Furthermore, Warp accepts Ultra37000 CPLDs VHDL or Verilog produced by the Active-HDL FSM graphical Finite State Machine editor. For simulation, Warp provides a FLASH370i CPLDs timing simulator, as well as VHDL and Verilog timing models MAX340 CPLDs for use with third party simulators. Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600 Document : 38-03046 Rev. *A Revised January 9, 2002 DESIGN COMPILATION VERFICA ENTRY TION CY3125 VHDL and Verilog Compilers The part of a Warp description that specifies the behavior or structure of the design is called an entity/architecture pair. VHDL and Verilog are powerful, industry standard languages Entity/architecture pairs, as their name implies, are divided for behavioral design entry and simulation, and are supported into two parts: an entity declaration, which declares the by all major vendors of EDA tools. They allow designers to designs interface signals (i.e., defines what external signals learn a single language that is useful for all facets of the design the design has, and what their directions and types are), and process. a design architecture, which describes the designs behavior VHDL and Verilog offer designers the ability to describe de- or structure. signs at many different levels. At the highest level, designs can The entity portion of a design file is a declaration of what a be entered as a description of their behavior. This behavioral design presents to the outside world (the interface). For each description is not tied to any specific target device. As a result, external signal, the entity declaration specifies a signal name, simulation can be done very early in the design to verify correct a direction and a data type. In addition, the entity declaration functionality, which significantly speeds the design process. specifies a name by which the entity can be referenced in a The Warp syntax for VHDL and Verilog includes support for design architecture. This section shows code segments from intermediate level entry modes such as state tables and Bool- five sample design files. The top portion of each example ean entry. At the lowest level, designs can be described using features the entity declaration. gate-level descriptions. Warp gives the designer the flexibility to intermix all of these entry modes. Behavioral Description In addition, Verilog and VHDL allow you to design hierarchical- The architecture portion of a design file specifies the function ly, building up entities in terms of other entities. This allows you of the design. As shown in Figure 1, multiple design-entry to work either top-down (designing the highest levels of the methods are supported in Warp. A behavioral description system and its interfaces first, then progressing to greater and in VHDL often includes well known constructs such as greater detail) or bottom-up (designing elementary building If...Then...Else, and Case statements. Here is a code blocks of the system, then combining these to build larger and segment from a simple state machine design (soda larger parts) with equal ease. vending machine) that uses behavioral VHDL to implement the design: Because these languages are IEEE standards, multiple ven- dors offer tools for design entry and simulation at both high and LIBRARY ieee low levels and synthesis of designs to different silicon targets. USE ieee.std logic 1164.all The use of device-independent behavioral design entry gives ENTITY drink IS users the freedom to easily migrate to high-volume technolo- PORT (nickel,dime,quarter,clock: in gies. The wide availability of VHDL and Verilog tools provides std logic complete vendor independence as well. Designers can begin returnDime,returnNickel,giveDrink:out their project using Warp for Cypress CPLDs and convert to high volume ASICs using the same VHDL or Verilog behav- std logic) ioral description with industry-standard synthesis tools. END drink The VHDL and Verilog languages also allow users to define their own functions. User-defined functions allow users to ex- tend the capabilities of the language and build reusable files of ARCHITECTURE fsm OF drink IS tested routines. VHDL and Verilog provide control over the tim- ing of events or processes. They have constructs that identify TYPE drinkState IS (zero,five,ten,fifteen, processes as either sequential, concurrent, or a combination twenty,twentyfive,owedime) of both. This is essential when describing the interaction of SIGNAL drinkstatus:drinkState complex state machines. BEGIN VHDL and Verilog are rich programming languages. Their flex- ibility reflects the nature of modern digital systems and allows PROCESS BEGIN designers to create accurate models of digital designs. Be- cause they are not verbose languages they are easy to learn WAIT UNTIL clock = 1 and compile. In addition, models created in VHDL and Verilog can readily be transported to other EDA Environments. Warp giveDrink <= 0 supports IEEE 1076/1164 VHDL including loops, for/gener- returnDime <= 0 ate statements, full hierarchical designs with packages, enu- returnNickel <= 0 merated types, and integers as well as IEEE 1364 Verilog including loops, reduction and conditional operators. CASE drinkStatus IS A VHDL Design Example WHEN zero => IF (nickel = 1) THEN Design Entry drinkStatus <= five ELSIF (dime = 1) THEN Warp descriptions specify: drinkStatus <= Ten The behavior or structure of a design, and ELSIF (quarter = 1) THEN The mapping of signals in a design to the pins of a drinkStatus <= twentyfive PLD/CPLD (optional) END IF WHEN five => Document : 38-03046 Rev. *A Page 2 of 8