CY7C245A 2K x 8 Reprogrammable Registered PROM Features Functional Description The CY7C245A is a high-performance, 2K x 8, electrically Windowed for reprogrammability programmable, read-only memory packaged in a slim 300-mil CMOS for optimum speed/power plastic or hermetic DIP. The ceramic package may be High speed equipped with an erasure window when exposed to UV light the PROM is erased and can then be reprogrammed. The 15-ns address set-up memory cells utilize proven EPROM floating-gate technology 10-ns clock to output and byte-wide intelligent programming algorithms. Low power The CY7C245A replaces bipolar devices and offers the advan- tages of lower power, reprogrammability, superior perfor- 330 mW (commercial) for -25 ns mance and high programming yield. The EPROM cell requires 660 mW (military) only 12.5V for the supervoltage, and low current requirements Programmable synchronous or asynchronous output allow gang programming. The EPROM cells allow each enable memory location to be tested 100%, because each location is written into, erased, and repeatedly exercised prior to encap- On-chip edge-triggered registers sulation. Each PROM is also tested for AC performance to Programmable asynchronous register (INIT) guarantee that after customer programming the product will EPROM technology, 100% programmable meet AC specification limits. Slim, 300-mil, 24-pin plastic or hermetic DIP The CY7C245A has an asynchronous initialize function (INIT). 5V 10% V , commercial and military This function acts as a 2049th 8-bit word loaded into the CC on-chip register. It is user programmable with any desired TTL-compatible I/O word, or may be used as a PRESET or CLEAR function on the Direct replacement for bipolar PROMs outputs. INIT is triggered by a low level, not an edge. Capable of withstanding greater than 2001V static discharge Logic Block Diagram Pin Configurations INIT DIP Top View 1 24 O A7 VCC A 0 2 A 23 6 A 8 7 A 1 3 22 A A 5 9 O 4 A A 21 2 4 A 10 ROW PROGRAMMABLE 6 MULTIPLEXER 5 A ADDRESS ARRAY A 20 INIT 3 3 O A 6 E/E 2 19 S A4 8-BIT 5 A 7 1 18 CP EDGE- A O 5 TRIGGERED A 0 8 17 O 7 ADDRESS REGISTER A 6 4 DECODER O 9 16 O 0 6 O O A 1 10 O 7 15 5 O 11 14 O 2 4 3 A 8 GND O 12 13 O 3 A 9 COLUMN 2 LCC/PLCC (Opaque only) Top View ADDRESS O A 10 1 321 2827 4 26 O CP A 25 10 A 5 4 PROGRAMMABLE A 24 INIT 3 6 MULTIPLEXER 0 E/E A 23 S DQ 2 7 E/E S A1 22 CP 8 C A 21 0 9 NC CP NC 20 10 O7 O 19 0 11 O 6 131415161718 12 Selection Guide 7C245A-15 7C245A-18 7C245A-25 7C245A-35 Unit Minimum Address Set-up Time 15 18 25 35 ns Maximum Clock to Output 10 12 12 15 ns Maximum Operating Current Standard Commercial 120 120 90 90 mA Military 120 120 120 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-04007 Rev. *E Revised August 17, 2006 + Feedback PROGRAMMABLE INITIALIZE WORD O 1 A 5 O 2 A 6 GND A 7 NC NC V O CC 3 A O 8 4 A 9 O 5CY7C245A on-chip register. Each bit is programmable and the initialize Operating Modes function can be used to load any desired combination of 1s The CY7C245A is a CMOS electrically programmable read and 0s into the register. In the unprogrammed state, activating only memory organized as 2048 words x 8 bits and is a INIT will generate a register CLEAR (all outputs LOW). If all pin-for-pin replacement for bipolar TTL fusible link PROMs. the bits of the initialize word are programmed, activating INIT The CY7C245A incorporates a D-type, master-slave register performs a register PRESET (all outputs HIGH). on chip, reducing the cost and size of pipelined micropro- Applying a LOW to the INIT input causes an immediate load grammed systems and applications where accessed PROM of the programmed initialize word into the master and slave data is stored temporarily in a register. Additional flexibility is flip-flops of the register, independent of all other inputs, provided with a programmable synchronous (E) or S including the clock (CP). The initialize data will appear at the asynchronous (E) output enable and asynchronous initial- device outputs after the outputs are enabled by bringing the ization (INIT). asynchronous enable (E) LOW. Upon power-up the state of the outputs will depend on the Erasure Characteristics programmed state of the enable function (E or E). If the S synchronous enable (E ) has been programmed, the register S Wavelengths of light less than 4000 Angstroms begin to erase will be in the set condition causing the outputs (O O ) to be 0 7 the 7C245A. For this reason, an opaque label should be in the OFF or high-impedance state. If the asynchronous placed over the window if the PROM is exposed to sunlight or enable (E) is being used, the outputs will come up in the OFF fluorescent lighting for extended periods of time. or high-impedance state only if the enable (E) input is at a HIGH logic level. Data is read by applying the memory location The recommended dose for erasure is ultraviolet light with a to the address inputs (A A ) and a logic LOW to the enable 0 10 wavelength of 2537 Angstroms for a minimum dose (UV input. The stored data is accessed and loaded into the master intensity multiplied by exposure time) of 25 Wsec/cm2. For an flip-flops of the data register during the address set-up time. At ultraviolet lamp with a 12 mW/cm2 power rating the exposure the next LOW-to-HIGH transition of the clock (CP), data is time would be approximately 35 minutes. The 7C245A needs transferred to the slave flip-flops, which drive the output to be within 1 inch of the lamp during erasure. Permanent buffers, and the accessed data will appear at the outputs damage may result if the PROM is exposed to high-intensity (O O ). 0 7 UV light for an extended period of time. 7258 Wsec/cm2 is the recommended maximum dosage. If the asynchronous enable (E) is being used, the outputs may be disabled at any time by switching the enable to a logic Programming Information HIGH, and may be returned to the active state by switching the enable to a logic LOW. Programming support is available from Cypress as well as If the synchronous enable (E ) is being used, the outputs will S from a number of third-party software vendors. For detailed go to the OFF or high-impedance state upon the next positive programming information, including a listing of software clock edge after the synchronous enable input is switched to packages, please see the PROM Programming Information a HIGH level. If the synchronous enable pin is switched to a located at the end of this section. Programming algorithms can logic LOW, the subsequent positive clock edge will return the be obtained from any Cypress representative. output to the active state. Following a positive clock edge, the address and synchronous enable inputs are free to change Bit Map Data since no change in the output will occur until the next low-to-high transition of the clock. This unique feature allows Programmer Address RAM Data the CY7C245A decoders and sense amplifiers to access the Decimal Hex Contents next location while previously addressed data remains stable 00 Data on the outputs System timing is simplified in that the on-chip edge triggered . register allows the PROM clock to be derived directly from the . system clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete 2047 7FF Data registers available in the market. 2048 800 Init Byte The CY7C245A has an asynchronous initialize input (INIT). 2049 801 Control Byte The initialize function is useful during power-up and time-out sequences and can facilitate implementation of other sophis- Control Byte ticated functions such as a built-in jump start address. When 00 Asynchronous output enable (default state) activated, the initialize control input causes the contents of a 01 Synchronous output enable user-programmed 2049th 8-bit word to be loaded into the Document : 38-04007 Rev. *E Page 2 of 13 + Feedback