CYP15G0101DXB CYV15G0101DXB Single-channel HOTLink II Transceiver Single-channel HOTLink II Transceiver Compatible with Features Fiber-optic modules Second-generation HOTLink technology Copper cables Circuit board traces Compliant to multiple standards ESCON , DVB-ASI, fibre channel and gigabit ethernet JTAG boundary scan (IEEE802.3z) Built-in self-test (BIST) for at-speed link testing CPRI compliant CYV15G0101DXB compliant to SMPTE 259M and SMPTE Per-channel link quality indicator 292M Analog signal detect 8B/10B encoded or 10-bit unencoded data Digital signal detect Single-channel transceiver operates from 195 to 1500 MBaud Low power 1.25 W at 3.3 V typical serial data rate Single 3.3 V supply Selectable parity check/generate 100-ball BGA Selectable input clocking options Pb-free package option available Selectable output clocking options 0.25 BiCMOS technology MultiFrame Receive Framer Bit and byte alignment Functional Description Comma or full K28.5 detect 1 The CYP15G0101DXB single-channel HOTLink II Single- or multi-byte framer for byte alignment transceiver is a point-to-point communications building block Low-latency option allowing the transfer of data over a high-speed serial link (optical Synchronous LVTTL parallel input and parallel output interface fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195 to 1500 MBaud. Internal phase-locked loops (PLLs) with no external PLL components The transmit channel accepts parallel characters in an input register, encodes each character for transport, and converts it to Dual differential PECL-compatible serial inputs serial data. The receive channel accepts serial data and converts Internal DC-restoration it to parallel data, frames the data to character boundaries, decodes the framed characters into data and special characters, Dual differential PECL-compatible serial outputs and presents these characters to an output register. Figure 1 Source matched for driving 50 transmission lines illustrates typical connections between independent host No external bias resistors required systems and corresponding CYP(V)15G0101DXB parts. As a Signaling-rate controlled edge-rates second-generation HOTLink device, the CYP(V)15G0101DXB extends the HOTLinkII family with enhanced levels of Optional elasticity buffer in receive path integration and faster data rates, while maintaining serial-link Optional phase align buffer in transmit path compatibility (data, command, and BIST) with other HOTLink devices. Figure 1. HOTLink II System Connections 10 10 10 Serial Link 10 Backplane or Cabled Connections Note 1. CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements. CYP(V)15G0101DXB refers both devices. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-02031 Rev. *P Revised November 9, 2017 System Host CYP(V)15G0101DXB CYP(V)15G0101DXB System HostCYP15G0101DXB CYV15G0101DXB The CYV15G0101DXB satisfies the SMPTE 259M and SMPTE The parallel I/O interface may be configured for numerous forms 292M compliance as per the EG34-1999 pathological test of clocking to provide the highest flexibility in system requirements. The transmit (TX) section of the architecture. In addition to clocking the transmit path interfaces CYP(V)15G0101DXB single-channel HOTLink II consists of a from one or multiple sources, the receive interface may be byte-wide channel. The channel can accept either eight-bit data configured to present data relative to a recovered clock or to a characters or pre-encoded 10-bit transmission characters. Data local reference clock. characters are passed from the transmit input register to an The transmit and the receive channels contain BIST pattern embedded 8B/10B encoder to improve their serial transmission generators and checkers, respectively. This BIST hardware characteristics. These encoded characters are then serialized allows at-speed testing of the high-speed serial data paths in and output from dual positive ECL (PECL)-compatible both transmit and receive sections, as well as across the differential transmission-line drivers at a bit-rate of either 10 or interconnecting links. 20 times the input reference clock. HOTLink II devices are ideal for a variety of applications where The receive (RX) section of the CYP(V)15G0101DXB parallel interfaces can be replaced with high-speed, single-channel HOTLink II consists of a byte-wide channel. The point-to-point serial links. Some applications include channel accepts a serial bit-stream from one of two interconnecting backplanes on switches, routers, base-stations, PECL-compatible differential line receivers and, using a servers and video transmission systems. completely integrated PLL clock synchronizer, recovers the The CYV15G0101DXB is verified by testing to be compliant to timing information necessary for data reconstruction. The all the pathological test patterns documented in SMPTE recovered bit-stream is deserialized and framed into characters, EG34-1999, for both the SMPTE 259M and 292M signaling 8B/10B decoded, and checked for transmission errors. rates. The tests ensure that the receiver recovers data with no Recovered decoded characters are then written to an internal errors for the following patterns: elasticity buffer, and presented to the destination host system. The integrated 8B/10B encoder/decoder may be bypassed for 1. Repetitions of 20 ones and 20 zeros. systems that present externally encoded or scrambled data at 2. Single burst of 44 ones or 44 zeros. the parallel interface. 3. Repetitions of 19 ones followed by 1 zero or 19 zeros followed by 1 one. Transceiver Logic Block Diagram x10 x11 Phase Elasticity Align Buffer Buffer Encoder Decoder 8B/10B 8B/10B Framer Serializer Deserializer RX TX Document Number: 38-02031 Rev. *P Page 2 of 45 OUT TXD 7:0 OUT2 TXCT 1:0 IN1 RXD 7:0 IN2 RXST 2:0