S29AL008J 8-Mbit (1M 8-Bit/512K 16-Bit), 3 V, Boot Sector Flash Distinctive Characteristics Architectural Advantages Performance Characteristics Single Power Supply Operation High Performance Full voltage range: 2.7 to 3.6 volt read and write operations Access times as fast as 55 ns for battery-powered applications Extended temperature range (40C to +125C) Manufactured on 110 nm Process Technology Automotive AEC-Q100 Grade 3 (40 C to +85 C) Fully compatible with 200 nm S29AL008D Automotive AEC-Q100 Grade 1 (40 C to +125 C) Secured Silicon Sector region Ultra Low Power Consumption (typical values at 5 MHz) 128-word/256-byte sector for permanent, secure 0.2 A Automatic Sleep mode current identification through an 8-word/16-byte random Electronic 0.2 A standby mode current Serial Number accessible through a command sequence 7 mA read current May be programmed and locked at the factory or by the 20 mA program/erase current customer Cycling Endurance: 1,000,000 cycles per sector typical Flexible Sector Architecture Data Retention: 20 years typical One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode) Package Options One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 48-ball Fine-pitch BGA Kword sectors (word mode) 48-pin TSOP Sector Group Protection Features A hardware method of locking a sector to prevent any Software Features program or erase operations within that sector CFI (Common Flash Interface) Compliant Sectors can be locked in-system or via programming Provides device-specific information to the system, equipment allowing host software to easily reconfigure for different Temporary Sector Unprotect feature allows code changes Flash devices in previously locked sectors Erase Suspend/Erase Resume Unlock Bypass Program Command Suspends an erase operation to read data from, or Reduces overall programming time when issuing multiple program data to, a sector that is not being erased, then program command sequences resumes the erase operation Top or Bottom Boot Block Configurations Available Data Polling and Toggle Bits Compatibility with JEDEC standards Provides a software method of detecting program or erase Pinout and software compatible with single-power supply operation completion Flash Superior inadvertent write protection Hardware Features Ready/Busy Pin (RY/BY ) Provides a hardware method of detecting program or erase cycle completion Hardware Reset Pin (RESET ) Hardware method to reset the device to reading array data WP input pin For boot sector devices: at V , protects first or last IL 16 Kbyte sector depending on boot configuration (top boot or bottom boot) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00778 Rev. *P Revised April 11, 2018S29AL008J General Description The S29AL008J is a 8 Mbit, 3.0 Volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball Fine-pitch BGA (0.8 mm pitch), and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15DQ0 the byte- wide (x8) data appears on DQ7DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt V CC supply. A 12.0 V V or 5.0 V are not required for write or erase operations. The device can also be programmed in standard PP CC EPROM programmers. The device offers access times of up to 55 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE ), write enable (WE ) and output enable (OE ) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The S29AL008J is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithman internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithman internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY pin, or by reading the DQ7 (Data Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V detector that automatically inhibits write operations during power CC transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. Cypress Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Document Number: 002-00778 Rev. *P Page 2 of 50