S6E1A11C0AGV20000

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com S6E1A Series 32-bit Arm Cortex -M0+ FM0+ Microcontroller The S6E1A Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power consumption and low cost. This series has the Arm Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of peripheral functions such as various timers, ADCs and communication interfaces (UART, CSIO, I2C, LIN). The products which are described in this data sheet are placed into TYPE1-M0+ product categories inFM0+ Family PERIPHERAL MANUA. Features CSIO 32-bit Arm Cortex-M0+ Core Full duplex double buffer Built-in dedicated baud rate generator Processor version: r0p1 Overrun error detection function Maximum operating frequency: 40 MHz Serial chip select function (ch.1 and ch.3 only) Nested Vectored Interrupt Controller (NVIC): 1 NMI Data length: 5 to 16 bits (non-maskable interrupt) and 32 peripheral interrupt with 4 LIN selectable interrupt priority levels LIN protocol Rev.2.1 supported 24-bit System timer (Sys Tick): System timer for OS task Full duplex double buffer management Master/Slave mode supported LIN break field generation function (The length is variable Bit Band operation between 13 bits and 16 bits.) Compatible with Cortex-M3 bit band operation LIN break delimiter generation function (The length is variable between 1 bit and 4 bits.) Various error detection functions available (parity errors, On-Chip Memories framing errors, and overrun errors) Flash memory 2 I C Up to 88 Kbyte Standard-mode (Max: 100 kbps) supported / Fast-mode Read cycle:0 wait-cycle (Max 400kbps) supported. Security function for code protection SRAM The on-chip SRAM of this series has one independent SRAM. SRAM: 6 Kbyte Multi-function Serial Interface (Max 3channels) 128 bytes with FIFO in all channels (The number of FIFO steps varies depending on the settings of the communication mode or bit length.) The operation mode of each channel can be selected from one of the following. UART CSIO LIN 2 I C UART Full duplex double buffer Parity can be enabled or disabled. Built-in dedicated baud rate generator External clock available as a serial clock Various error detection functions (parity errors, framing errors, and overrun errors) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-05091 Rev. *D Revised June 24, 2019