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Clock/Timing-Application Specific CABGA-144 RoHS
Manufacturer: Integrated Device Tech

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Integrated Device Tech

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Integrated Device Tech
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Timers & Support Products
Timers Support Products
CABGA - 144
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Integrated Device Tech
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Synchronous Equipment Timing Source 82P33731 for 10G/40G/100G Synchronous Ethernet Datasheet (SEC) and Telcordia GR-253-CORE/ GR-1244-CORE for Stratum 3 HIGHLIGHTS and SONET Minimum Clock (SMC) Synchronous Equipment Timing Source (SETS) for Synchronous DPLL1 generates clocks with PDH, TDM, GSM, CPRI/OBSAI, 10/100/ Ethernet (SyncE) per ITU-T G.8264 1000 Ethernet and GNSS frequencies these clocks are directly avail- DPLL1 generates ITU-T G.8262 compliant SyncE clocks, Telcordia able on OUT1 GR-1244-CORE/GR-253-CORE, and ITU-T G.813 compliant SONET/ DPLL2 generates N x 8 kHz clocks up to 100 MHz that are output on SDH clocks OUT9 and OUT10 DPLL2 performs rate conversions for synchronization interfaces or for APLL1, APLL2 and APLL3 are connected to DPLL1 other general purpose timing applications APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or APLL3 is Voltage Controlled Crystal Oscillator (VCXO) based and SONET/SDH frequencies generates clocks with jitter <0.3 ps RMS (10 kHz to 20 MHz) for: APLL3 generates 10G/40G/100G Ethernet, WAN-PHY, and LAN-PHY 10GBASE-R, 10GBASE-W, 40GBASE-R and 100GBASE-R frequencies APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to Any of eight common TCXO/OCXO frequencies can be used for the 20 MHz) for: 1000BASE-T and 1000BASE-X System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, Fractional-N input dividers support a wide range of reference frequen- 24.576 MHz, 25 MHz, or 30.72 MHz cies The I2C slave interface can be used by a host processor to access the Locks to 1 Pulse Per Second (PPS) references control and status registers DPLLs, APLL1 and APLL2 can be configured from an external The I2C master interface can automatically load a device configura- EEPROM after reset tion from an external EEPROM after reset APLL3 must be configured FEATURES via the I2C slave interface Composite clock inputs (IN1 and IN2) accept 64 kHz synchronization DPLLs can be connected to an internal composite clock generator that interface signals per ITU-T G.703 outputs its 64 kHz synchronization signal on OUT8 Differential reference inputs (IN3 to IN8) accept clock frequencies Differential outputs OUT3 to OUT6 output clocks with frequencies between 1 PPS and 650 MHz between 1 PPS and 650 MHz Single ended inputs (IN9 to IN14) accept reference clock frequencies Differential outputs OUT11 and OUT12 output clocks with frequencies between 1 PPS and 162.5 MHz up to 650 MHz Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any Single ended outputs OUT1, OUT2 and OUT7 output clocks with fre- clock reference input quencies between 1 PPS and 125 MHz Reference monitors qualify/disqualify references depending on activ- Single ended outputs OUT9 and OUT10 output clocks N*8 kHz multi- ity, frequency and LOS pins ples up to 100 MHz Automatic reference selection state machines select the active refer- DPLL1 supports independent programmable delays for each of IN3 to ence for each DPLL based on the reference monitors, priority tables, IN14 the delay for each input is programmable in steps of 0.61 ns revertive and non-revertive settings and other programmable settings with a range of ~78 ns Fractional-N input dividers enable the DPLLs to lock to a wide range The input to output phase delay of DPLL1 is programmable in steps of of reference clock frequencies including: 10/100/1000 Ethernet, 10G/ 0.0745 ps with a total range of 20 s 40G/100G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI, The clock phase of each of the output dividers for OUT1 (from APLL1) and GNSS frequencies to OUT7 is individually programmable in steps of ~200 ps with a total Any reference inputs (IN3 to IN14) can be designated as external sync range of +/-180 pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a select- 1149.1 JTAG Boundary Scan able reference clock input 144-pin CABGA green package FRSYNC 8K 1PPS and MFRSYNC 2K 1PPS output sync pulses APPLICATIONS that are aligned with the selected external input sync pulse input and Access routers, edge routers, core routers frequency locked to the associated reference clock input Carrier Ethernet switches DPLL1 can be configured with bandwidths between 0.09 mHz and Multi-service access platforms 567 Hz PON OLT DPLL1 locks to input references with frequencies between 1 PPS and LTE eNodeB 650 MHz ITU-T G.8264 Synchronous Equipment Timing Source (SETS) DPLL2 locks to input references with frequencies between 8 kHz and ITU-T G.8262 Synchronous Ethernet Equipment Clock (EEC) 650 MHz ITU-T G.813 Synchronous Equipment Clock (SEC) DPLL1 complies with ITU-T G.8262 for Synchronous Ethernet Equip- Telcordia GR-253-CORE/GR1244-CORE Stratum 3 Clock (S3) and ment Clock (EEC), and G.813 for Synchronous Equipment Clock SONET Minimum Clock (SMC) 2017 Integrated Device Technology, Inc. 1 August 28, 201782P33731 Datasheet DESCRIPTION The 82P33731 Synchronous Equipment Timing Source (SETS) for 10G Synchronous Ethernet (SyncE) provides tools to manage timing refer- ences, clock generation and timing paths for SyncE based clocks, per ITU-T G.8264 and ITU-T G.8262. 82P33731 meets the requirements of ITU-T G.8262 for synchronous Ethernet Equipment Clocks (EECs) and ITU-T G.813 for Synchronous Equipment Clocks (SEC). The device outputs low-jit- ter clocks that can directly synchronize 100GBASE-R, 40GBASE-R, 10GBASE-R and 10GBASE-W and lower-rate Ethernet interfaces as well as CPRI/OBSAI, SONET/SDH and PDH interfaces. The 82P33731 accepts six differential reference inputs and six single ended reference inputs that can operate at common GNSS, Ethernet, SONET/SDH and PDH frequencies that range from 1 Pulse Per Second (PPS) to 650 MHz. The device also provides two Alternate Mark Inversion (AMI) inputs for Composite Clock (CC) signals bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The references are continually moni- tored for loss of signal and for frequency offset per user programmed thresholds. All of the references are available to both Digital PLLs (DPLLs). The active reference for each DPLL is determined by forced selection or by automatic selection based on user programmed priorities and locking allow- ances and based on the reference monitors and LOS inputs. The 82P33731 can accept a clock reference and an associated phase locked sync signal as a pair. DPLL1 can lock to the clock reference and align the frame sync and multi-frame sync outputs with the paired sync input. The device allows any of the differential or single ended reference inputs to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. The input sync signals can have a frequency of 1 PPS, 2 kHz, 4 kHz or 8 kHz. This feature enables DPLL1 to phase align its frame sync and multi-frame sync outputs with a sync input without the need use a low bandwidth setting to lock directly to the sync input. The DPLLs support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode the DPLLs synthesize clocks based on the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term output fre- quency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL uses frequency data acquired while in Locked mode to generate accurate frequencies when input references are not available. The 82P33731 requires a system clock for its reference monitors and other digital circuitry. The frequency accuracy of the system clock deter- mines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequency stability of the DPLLs in Free-Run mode and in Holdover mode and it affects the wander generation of the DPLLs in Locked mode. When used with a suitable system clock, DPLL1 meets the frequency accuracy, pull-in, hold-in, pullout, noise generation, noise tolerance, tran- sient response, and holdover performance requirements of the following applications: ITU-T G.8262/G.813 EEC/SEC options 1 and 2, Telcordia GR- 1244 Stratum 3 (S3), Telcordia GR-253-CORE S3 and SONET Minimum Clock (SMC). DPLL1 can be configured with a range of selectable filtering bandwidths from 0.09 mHz to 567 Hz. The 17 mHz bandwidth can be used to lock the DPLL directly to a 1 PPS reference. The 92 mHz bandwidth can be used for G.8262/G.813 Option 2, or Telcordia GR-253-CORE S3, or SMC applica- tions. The bandwidths in the range 1.1 Hz to 8.9 Hz can be used for G.8262/G.813 Option 1 applications. The bandwidth of 1.1 Hz or 2.2 Hz can be used for Telcordia GR-1244-CORE S3 applications. Bandwidths above 10 Hz can be used in jitter attenuation and rate conversion applications. DPLL2 is a wideband (BW > 25Hz) frequency translator that can be used, for example, to convert a recovered line clock to a 1.544 MHz or 2.048 MHz synchronization interface clock. For SETS applications per ITU-T G.8264, DPLL1 is configured as an EEC/SEC to output clocks for the T0 reference point and DPLL2 is used to output clocks for the T4 reference point. Clocks generated by DPLL1 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The output clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces. Clocks generated by DPLL1 can be passed through APLL3 which is a voltage controlled crystal oscillator (VCXO) based jitter attenuating APLL. APLL3 can be provisioned with one or two selectable crystal resonators to support up to two base frequencies. The output clocks generated by APLL3 are suitable for multi-lane 100GBASE-R, 40GBASE-R and lower rate interfaces. The device provides an AMI output for a CC signal bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The CC output can be con- nected to either DPLL1 or DPLL3. All 82P33731 control and status registers are accessed through an I2C slave microprocessor interface. For configuring the DPLLs, APLL1 and APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset. APLL3 must be configured via the I2C slave interface. 2017 Integrated Device Technology, Inc. 2 August 28, 2017

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits