FLEX 10KE Embedded Programmable Logic Device January 2003, ver. 2.5 Data Sheet Embedded programmable logic devices (PLDs), providing Features... system-on-a-programmable-chip (SOPC) integration in a single device Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions Dual-port capability with up to 16-bit width per embedded array block (EAB) Logic array for general logic functions High density 30,000 to 200,000 typical gates (see Tables 1 and 2) Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity System-level features TM MultiVolt I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices Low power consumption Bidirectional I/O performance (t and t ) up to 212 MHz SU CO Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2, for 5.0-V operation Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic For information on 5.0-V FLEX 10K or 3.3-V FLEX 10KA devices, see the f FLEX 10K Embedded Programmable Logic Family Data Sheet. Table 1. FLEX 10KE Device Features Feature EPF10K30E EPF10K50E EPF10K50S Typical gates (1) 30,000 50,000 Maximum system gates 119,000 199,000 Logic elements (LEs) 1,728 2,880 EABs 6 10 Total RAM bits 24,576 40,960 Maximum user I/O pins 220 254 Altera Corporation 1 DS-F10KE-2.5FLEX 10KE Embedded Programmable Logic Devices Data Sheet Table 2. FLEX 10KE Device Features Feature EPF10K100E (2) EPF10K130E EPF10K200E EPF10K200S Typical gates (1) 100,000 130,000 200,000 Maximum system gates 257,000 342,000 513,000 Logic elements (LEs) 4,992 6,656 9,984 EABs 12 16 24 Total RAM bits 49,152 65,536 98,304 Maximum user I/O pins 338 413 470 Note to tables: (1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum system gates. (2) New EPF10K100B designs should use EPF10K100E devices. Fabricated on an advanced process and operate with a 2.5-V ...and More internal supply voltage Features In-circuit reconfigurability (ICR) via external configuration devices, intelligent controller, or JTAG port TM TM ClockLock and ClockBoost options for reduced clock delay/skew and clock multiplication Built-in low-skew clock distribution trees 100% functional testing of all devices test vectors or scan chains are not required Pull-up on I/O pins before and during configuration Flexible interconnect FastTrack Interconnect continuous routing structure for fast, predictable interconnect delays Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) Tri-state emulation that implements internal tri-state buses Up to six global clock signals and four global clear signals Powerful I/O pins Individual tri-state output enable control for each pin Open-drain option on each I/O pin Programmable output slew-rate control to reduce switching noise Clamp to V user-selectable on a pin-by-pin basis CCIO Supports hot-socketing 2 Altera Corporation