MAX 7000
Programmable Logic
Device Family
September 2005, ver. 6.7 Data Sheet
High-performance, EEPROM-based programmable logic devices
Features...
(PLDs) based on second-generation MAX architecture
5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
ISP circuitry compatible with IEEE Std. 1532
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S
devices with 128 or more macrocells
Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see Tables 1 and 2)
5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
PCI-compliant devices available
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
f
MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family
Data Sheet or the MAX 7000B Programmable Logic Device Family Data
Sheet.
Table 1. MAX 7000 Device Features
Feature EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E
Usable 600 1,250 1,800 2,500 3,200 3,750 5,000
gates
Macrocells 32 64 96 128 160 192 256
Logic array 246 8 10 12 16
blocks
Maximum 36 68 76 100 104 124 164
user I/O pins
t (ns) 6 6 7.5 7.5 10 12 12
PD
t (ns) 5 5 6677 7
SU
t (ns) 2.5 2.5 3333 3
FSU
t (ns) 4 4 4.5 4.5 5 6 6
CO1
f (MHz) 151.5 151.5 125.0 125.0 100.0 90.9 90.9
CNT
Altera Corporation 1
DS-MAX7000-6.7MAX 7000 Programmable Logic Device Family Data Sheet
Table 2. MAX 7000S Device Features
Feature EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S
Usable gates 600 1,250 2,500 3,200 3,750 5,000
Macrocells 32 64 128 160 192 256
Logic array 24 8 10 12 16
blocks
Maximum 36 68 100 104 124 164
user I/O pins
t (ns) 5 5 6 6 7.5 7.5
PD
t (ns) 2.9 2.9 3.4 3.4 4.1 3.9
SU
t (ns) 2.5 2.5 2.5 2.5 3 3
FSU
t (ns) 3.2 3.2 4 3.9 4.7 4.7
CO1
f (MHz) 175.4 175.4 147.1 149.3 125.0 128.2
CNT
Open-drain output option in MAX 7000S devices
...and More
Programmable macrocell flipflops with individual clear, preset,
Features
clock, and clock enable controls
Programmable power-saving mode for a reduction of over 50% in
each macrocell
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic
pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
Programmable security bit for protection of proprietary designs
3.3-V or 5.0-V operation
TM
MultiVolt I/O interface operation, allowing devices to
interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is
not available in 44-pin packages)
Pin compatible with low-voltage MAX 7000A and MAX 7000B
devices
Enhanced features available in MAX 7000E and MAX 7000S devices
Six pin- or logic-driven output enable signals
Two global clock signals with optional inversion
Enhanced interconnect resources for improved routability
Fast input setup times provided by a dedicated path from I/O
pin to macrocell registers
Programmable output slew-rate control
Software design support and automatic place-and-route provided by
Alteras development system for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
2 Altera Corporation