MAX 9000
Includes
MAX 9000A
Programmable Logic
Device Family
June 2003, ver. 6.5 Data Sheet
High-performance CMOS EEPROM-based programmable logic
Features...
devices (PLDs) built on third-generation Multiple Array MatriX
(MAX ) architecture
5.0-V in-system programmability (ISP) through built-in IEEE Std.
1149.1 Joint Test Action Group (JTAG) interface
Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE
Std. 1149.1-1990
High-density erasable programmable logic device (EPLD) family
ranging from 6,000 to 12,000 usable gates (see Table 1)
10-ns pin-to-pin logic delays with counter frequencies of up to
144 MHz
Fully compliant with the peripheral component interconnect Special
Interest Groups (PCI SIG) PCI Local Bus Specification, Revision 2.2
Dual-output macrocell for independent use of combinatorial and
registered logic
FastTrack Interconnect for fast, predictable interconnect delays
Input/output registers with clear and clock enable on all I/O pins
Programmable output slew-rate control to reduce switching noise
MultiVolt I/O interface operation, allowing devices to interface with
3.3-V and 5.0-V devices
Configurable expander product-term distribution allowing up to 32
product terms per macrocell
Programmable power-saving mode for more than 50% power
reduction in each macrocell
Table 1. MAX 9000 Device Features
Feature EPM9320 EPM9400 EPM9480 EPM9560
EPM9320A EPM9560A
Usable gates 6,000 8,000 10,000 12,000
Flipflops 484 580 676 772
Macrocells 320 400 480 560
Logic array blocks (LABs) 20 25 30 35
Maximum user I/O pins 168 159 175 216
t (ns) 10 15 10 10
PD1
t (ns) 3.0 5 3.0 3.0
FSU
t (ns) 4.5 7 4.8 4.8
FCO
f (MHz) 144 118 144 144
CNT
Altera Corporation 1
DS-M9000-6.5MAX 9000 Programmable Logic Device Family Data Sheet
Programmable macrocell flipflops with individual clear, preset,
...and More
clock, and clock enable controls
Features
Programmable security bit for protection of proprietary designs
Software design support and automatic place-and-route provided by
Alteras MAX+PLUS II development system on Windows-based
PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM
RISC System/6000 workstations
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
Programming support with Alteras Master Programming Unit
TM TM
(MPU), BitBlaster serial download cable, ByteBlaster parallel
TM
port download cable, and ByteBlasterMV parallel port download
cable, as well as programming hardware from third-party
manufacturers
Offered in a variety of package options with 84 to 356 pins (see
Table 2)
Table 2. MAX 9000 Package Options & I/O Counts Note (1)
Device 84-Pin 208-Pin 240-Pin 280-Pin 304-Pin 356-Pin
PLCC RQFP RQFP PGA RQFP BGA
EPM9320 60 (2) 132 168 168
EPM9320A 60 (2) 132 168
EPM9400 59 (2) 139 159
EPM9480 146 175
EPM9560 153 191 216 216 216
EPM9560A 153 191 216
Notes:
(1) MAX 9000 device package types include plastic J-lead chip carrier (PLCC), power
quad flat pack (RQFP), ceramic pin-grid array (PGA), and ball-grid array (BGA)
packages.
(2) Perform a complete thermal analysis before committing a design to this device
package. See Application Note 74 (Evaluating Power for Altera Devices).
2 Altera Corporation