DDR3-E5-UT Lattice

Double Data Rate (DDR3) SDRAM Controller IP Core User Guide IPUG80 Version 1.9, October 2016Table of Contents Chapter 1. Introduction .......................................................................................................................... 5 Quick Facts ........................................................................................................................................................... 5 Features ................................................................................................................................................................ 6 Chapter 2. Functional Description ........................................................................................................ 8 Overview ............................................................................................................................................................... 8 DDR3 MC Module ................................................................................................................................................. 9 Command Decode Logic.............................................................................................................................. 9 Command Application Logic ........................................................................................................................ 9 On-Die Termination...................................................................................................................................... 9 DDR3 PHY Module ............................................................................................................................................... 9 Initialization Module............................................................................................................................................. 10 Write Leveling ............................................................................................................................................ 10 Read Training (Only for ECP5 Device) ...................................................................................................... 10 Selecting READ PULSE TAP Value (Only for LatticeECP3 Device) ................................................................ 11 Data Path Logic.......................................................................................................................................... 11 Signal Descriptions ............................................................................................................................................. 11 Using the Local User Interface............................................................................................................................ 14 Initialization Control.................................................................................................................................... 14 Command and Address ............................................................................................................................. 15 User Commands ........................................................................................................................................ 16 WRITE........................................................................................................................................................ 16 WRITEA ..................................................................................................................................................... 17 READ ......................................................................................................................................................... 17 READA....................................................................................................................................................... 18 REFRESH Support .................................................................................................................................... 18 Local-to-Memory Address Mapping .................................................................................................................... 19 Mode Register Programming .............................................................................................................................. 19 Chapter 3. Parameter Settings ............................................................................................................ 21 Type Tab............................................................................................................................................................. 23 Select Memory ........................................................................................................................................... 24 RefClock (Only for ECP5 DDR3 IP)........................................................................................................... 24 Clock (for ECP3) MemClock (for ECP5) .................................................................................................... 24 Memory Type ............................................................................................................................................. 24 Memory Data Bus Size .............................................................................................................................. 24 Configuration.............................................................................................................................................. 24 DIMM Type or Chip Select Width............................................................................................................... 24 Address Mirror............................................................................................................................................ 24 Clock Width................................................................................................................................................ 24 CKE Width.................................................................................................................................................. 25 2T MODE ................................................................................................................................................... 25 Data rdy to Write Data Delay .................................................................................................................... 25 Write Leveling ............................................................................................................................................ 25 Controller Reset to Memory ....................................................................................................................... 25 Setting Tab.......................................................................................................................................................... 25 Row Size.................................................................................................................................................... 26 Column Size............................................................................................................................................... 26 Auto Refresh Burst Count .......................................................................................................................... 26 External Auto Refresh Port ........................................................................................................................ 26 Burst Length............................................................................................................................................... 26 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG80 1.9, October 2016 2 DDR3 SDRAM Controller IP Core Users Guide