FFT-COMP-PM-U2 Lattice

FFT Compiler IP Core Users Guide August 2011 IPUG54_01.9Table of Contents Chapter 1. Introduction .......................................................................................................................... 4 Quick Facts ........................................................................................................................................................... 4 Features ................................................................................................................................................................ 6 Chapter 2. Functional Description ........................................................................................................ 8 Block Diagram....................................................................................................................................................... 8 High Performance Architecture.................................................................................................................... 9 Low Resource Architecture.......................................................................................................................... 9 Configuring the FFT Compiler............................................................................................................................. 10 Number of Points ....................................................................................................................................... 10 Architecture................................................................................................................................................ 10 Output Order .............................................................................................................................................. 10 Scaling Mode ............................................................................................................................................. 11 Precision Reduction Method ...................................................................................................................... 11 Signal Descriptions ............................................................................................................................................. 11 Interfacing with the FFT Compiler....................................................................................................................... 12 Configuration Signals................................................................................................................................. 12 Handshake Signals .................................................................................................................................... 13 Exponent Output ........................................................................................................................................ 13 Exceptions.................................................................................................................................................. 13 Timing Specifications .......................................................................................................................................... 13 Chapter 3. Parameter Settings ............................................................................................................ 16 Points/Mode Tab ................................................................................................................................................. 17 Number of Points ....................................................................................................................................... 17 Architecture................................................................................................................................................ 17 FFT Mode................................................................................................................................................... 17 Output Order .............................................................................................................................................. 18 Scaling Width Tab............................................................................................................................................... 18 Scaling Mode ............................................................................................................................................. 18 Data Width ................................................................................................................................................. 18 Precision Reduction Method ...................................................................................................................... 19 Implementation Tab ............................................................................................................................................ 19 Multiplier Type............................................................................................................................................ 19 Pipeline ...................................................................................................................................................... 19 Memory Type ............................................................................................................................................. 19 Synthesis and Simulation Tools Tab................................................................................................................... 20 Support Synplify......................................................................................................................................... 20 Support Precision....................................................................................................................................... 20 Support ModelSim...................................................................................................................................... 20 Support ALDEC.......................................................................................................................................... 20 Chapter 4. IP Core Generation............................................................................................................. 21 Licensing the IP Core.......................................................................................................................................... 21 Getting Started.................................................................................................................................................... 21 IPexpress-Created Files and Top Level Directory Structure............................................................................... 24 Instantiating the Core.......................................................................................................................................... 25 Running Functional Simulation ........................................................................................................................... 25 Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 25 Hardware Evaluation........................................................................................................................................... 26 Enabling Hardware Evaluation in Diamond................................................................................................ 26 Enabling Hardware Evaluation in ispLEVER.............................................................................................. 26 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG54_01.9, August 2011 2 FFT Compiler IP Core Users Guide