ICE5LP2K-SWG36ITR50 Lattice

iCE40 Ultra Family Data Sheet FPGA-DS-02028-2.3 August 2018 iCE40 Ultra Family Data Sheet Contents Acronyms in This Document ................................................................................................................................................. 5 1. General Description ...................................................................................................................................................... 6 1.1. Features ............................................................................................................................................................... 6 2. Product Family .............................................................................................................................................................. 7 2.1. Overview ............................................................................................................................................................. 7 3. Architecture .................................................................................................................................................................. 8 3.1. Architecture Overview ........................................................................................................................................ 8 3.1.1. PLB Blocks ....................................................................................................................................................... 9 3.1.2. Routing .......................................................................................................................................................... 10 3.1.3. Clock/Control Distribution Network ............................................................................................................. 10 3.1.4. sysCLOCK Phase Locked Loops (PLLs)............................................................................................................ 10 3.1.5. sysMEM Embedded Block RAM Memory ..................................................................................................... 12 3.1.6. sysDSP ........................................................................................................................................................... 14 3.1.7. sysIO Buffer Banks ........................................................................................................................................ 18 3.1.8. sysIO Buffer ................................................................................................................................................... 21 3.1.9. On-Chip Oscillator ......................................................................................................................................... 22 2 3.1.10. User I C IP ................................................................................................................................................. 22 3.1.11. User SPI IP ................................................................................................................................................. 22 3.1.12. High Current LED Drive I/O Pins ............................................................................................................... 22 3.1.13. Embedded PWM IP ................................................................................................................................... 23 3.1.14. Non-Volatile Configuration Memory ........................................................................................................ 23 3.2. iCE40 Ultra Programming and Configuration .................................................................................................... 24 3.2.1. Device Programming ..................................................................................................................................... 24 3.2.2. Device Configuration..................................................................................................................................... 24 3.2.3. Power Saving Options ................................................................................................................................... 24 4. DC and Switching Characteristics ................................................................................................................................ 25 4.1. Absolute Maximum Ratings .............................................................................................................................. 25 4.2. Recommended Operating Conditions ............................................................................................................... 25 4.3. Power Supply Ramp Rates ................................................................................................................................. 26 4.4. Power-On Reset ................................................................................................................................................ 26 4.5. Power-up Supply Sequence ............................................................................................................................... 26 4.6. External Reset ................................................................................................................................................... 26 4.7. Power-On-Reset Voltage Levels ........................................................................................................................ 27 4.8. ESD Performance ............................................................................................................................................... 28 4.9. DC Electrical Characteristics .............................................................................................................................. 28 4.10. Supply Current ................................................................................................................................................... 29 2 4.11. User I C Specifications ....................................................................................................................................... 29 4.12. User SPI Specifications ...................................................................................................................................... 30 4.13. Internal Oscillators (HFOSC, LFOSC) .................................................................................................................. 30 4.14. sysI/O Recommended Operating Conditions .................................................................................................... 30 4.15. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 31 4.16. Differential Comparator Electrical Characteristics ............................................................................................ 31 4.17. Typical Building Block Function Performance ................................................................................................... 31 4.17.1. Pin-to-Pin Performance (LVCMOS25) ....................................................................................................... 31 4.17.2. Register-to-Register Performance ............................................................................................................ 32 4.18. Derating Logic Timing ........................................................................................................................................ 32 4.19. Maximum sysIO Buffer Performance ................................................................................................................ 32 4.20. iCE40 Ultra Family Timing Adders ..................................................................................................................... 33 4.21. iCE40 Ultra External Switching Characteristics.................................................................................................. 33 4.22. sysCLOCK PLL Timing ......................................................................................................................................... 34 4.23. sysDSP Timing .................................................................................................................................................... 35 4.24. SPI Master or NVCM Configuration Time .......................................................................................................... 35 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02028-2.3