Product Information

ISPLSI 5256VE-125LT128

ISPLSI 5256VE-125LT128 electronic component of Lattice

Datasheet
CPLD ispLSI® 5000VE Family 12K Gates 256 Macro Cells 125MHz 3.3V 128-Pin TQFP

Manufacturer: Lattice
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 57 ea
Line Total: USD 57

5448 - Global Stock
Ships to you between
Fri. 05 Apr to Thu. 11 Apr
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
5448 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 1
Multiples : 1
1 : USD 57
10 : USD 51.3
50 : USD 34.2
100 : USD 25.65
500 : USD 20.525
1000 : USD 19.7375
2500 : USD 19
5000 : USD 18.325

5448 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 5001
Multiples : 1
5001 : USD 18.325

     
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Input Bus Input Bus Generic Generic Logic Block Logic Block ispLSI 5256VE In-System Programmable 3.3V SuperWIDE High Density PLD Features Functional Block Diagram Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE Input Bus Input Bus Boundary 3.3V Power Supply Scan Generic Generic Interface User Selectable 3.3V/2.5V I/O Logic Block Logic Block 12000 PLD Gates / 256 Macrocells Up to 144 I/O Pins 256 Registers High-Speed Global Interconnect SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. Global Routing Pool (GRP) PCB Efficient Ball Grid Array (BGA) Package Options Interfaces with Standard 5V TTL Devices 2 HIGH PERFORMANCE E CMOS TECHNOLOGY fmax = 165 MHz Maximum Operating Frequency tpd = 6.0 ns Propagation Delay TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels Electrically Erasable and Reprogrammable Generic Generic Non-Volatile Logic Block Logic Block Programmable Speed/Power Logic Path Optimization Input Bus Input Bus IN-SYSTEM PROGRAMMABLE Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality ispLSI 5000VE Description Reprogram Soldered Devices for Faster Debugging 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND The ispLSI 5000VE Family of In-System Programmable 3.3V IN-SYSTEM PROGRAMMABLE High Density Logic Devices is based on Generic Logic ARCHITECTURE FEATURES Blocks (GLBs) of 32 registered macrocells and a single Enhanced Pin-Locking Architecture with Single- Global Routing Pool (GRP) structure interconnecting the Level Global Routing Pool and SuperWIDE GLBs GLBs. Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell Outputs from the GLBs drive the Global Routing Pool Macrocells Support Concurrent Combinatorial and (GRP) between the GLBs. Switching resources are pro- Registered Functions vided to allow signals in the Global Routing Pool to drive Macrocell Registers Feature Multiple Control any or all the GLBs in the device. This mechanism allows Options Including Set, Reset and Clock Enable fast, efficient connections across the entire device. Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks Each GLB contains 32 macrocells and a fully populated, Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options programmable AND-array with 160 logic product terms Four Global Product Term Output Enables, Two and three extra control product terms. The GLB has 68 Global OE Pins and One Product Term OE per inputs from the Global Routing Pool which are available Macrocell in both true and complement form for every product term. The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be by- passed for functions of five product terms or less. The three extra product terms are used for shared controls: reset, clock, clock enable and output enable. Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Input Bus Input Bus Generic Generic Logic Block Logic Block Specifications ispLSI 5256VE Functional Block Diagram Figure 1. ispLSI 5256VE Functional Block Diagram (144-I/O Option) Input Bus Input Bus TDI Boundary Scan TDO Generic Generic Interface VCCIO Logic Block Logic Block 1 TOE I/O 107 I/O 1 I/O 106 I/O 2 I/O 105 I/O 3 I/O 104 I/O 14 I/O 93 I/O 15 I/O 92 I/O 16 I/O 91 I/O 17 I/O 90 Global Routing Pool I/O 18 I/O 89 I/O 19 (GRP) I/O 88 I/O 20 I/O 87 I/O 21 I/O 86 I/O 75 I/O 32 I/O 74 I/O 33 I/O 73 I/O 34 I/O 72 I/O 35 Generic Generic Logic Block Logic Block Input Bus Input Bus RESET 1. CLK2, CLK3 and TOE signals are shared with I/O signals. Use the table below to determine which I/O is shared by package type. Package Type Multplexed Signals 100 TQFP 1/O 44 / CLK2 I/O 49 / CLK 3 I/O 0 / TOE 128 TQFP I/O 59 / CLK2 I/O 65 / CLK3 I/O 0 / TOE 256 fpBGA I/O 119 / CLK2 I/O 131 / CLK3 I/O 0 / TOE 272 BGA I/O 119 / CLK2 I/O 131 / CLK3 I/O 0 / TOE 2 GOE0 Input Bus Input Bus GOE1 Generic Generic Logic Block Logic Block I/O 36 I/O 143 I/O 37 I/O 142 I/O 38 I/O 141 I/O 39 I/O 140 I/O 50 I/O 129 I/O 51 I/O 128 I/O 52 I/O 127 I/O 53 I/O 126 I/O 54 I/O 125 I/O 55 I/O 124 I/O 56 I/O 123 I/O 57 I/O 122 I/O 68 I/O 111 I/O 69 I/O 110 I/O 70 I/O 109 I/O 71 I/O 108 CLK 0 CLK 1 TCK 1 CLK 2 1 CLK 3 TMS

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:
LA4
LAT
LATTICE SEMI
Lattice Semiconductor
Lattice Semiconductor Corporation
Vantis

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