LAE5UM-45F-7BG381E Lattice

ECP5 Automotive Family Data Sheet FPGA-DS-02014 -1.1 June 2018 ECP5 Automotive Family Data Sheet Contents Acronyms in This Document ................................................................................................................................................. 7 1. General Description ...................................................................................................................................................... 8 1.1. Features ............................................................................................................................................................... 8 2. Architecture ................................................................................................................................................................ 10 2.1. Overview ........................................................................................................................................................... 10 2.2. PFU Blocks ......................................................................................................................................................... 11 2.2.1. Slice ............................................................................................................................................................... 12 2.2.2. Modes of Operation ...................................................................................................................................... 15 2.3. Routing .............................................................................................................................................................. 16 2.4. Clocking Structure ............................................................................................................................................. 16 2.5. sysCLOCK PLL ..................................................................................................................................................... 16 2.6. Clock Distribution Network ............................................................................................................................... 18 2.7. Primary Clocks ................................................................................................................................................... 18 2.8. Dynamic Clock Control ...................................................................................................................................... 19 2.9. Dynamic Clock Select ......................................................................................................................................... 19 2.10. Edge Clock ......................................................................................................................................................... 19 2.11. Clock Dividers .................................................................................................................................................... 20 2.12. DDRDLL .............................................................................................................................................................. 21 2.13. sysMEM Memory .............................................................................................................................................. 22 2.13.1. sysMEM Memory Block ............................................................................................................................ 22 2.13.2. Bus Size Matching ..................................................................................................................................... 23 2.13.3. RAM Initialization and ROM Operation .................................................................................................... 23 2.13.4. Memory Cascading ................................................................................................................................... 23 2.13.5. Single, Dual and Pseudo-Dual Port Modes ............................................................................................... 23 2.13.6. Memory Core Reset .................................................................................................................................. 24 2.14. sysDSP Slice .................................................................................................................................................... 25 2.14.1. sysDSP Slice Approach Compared to General DSP ................................................................................... 25 2.15. ECP5 Automotive sysDSP Slice Architecture Features ...................................................................................... 26 2.16. Programmable I/O Cells .................................................................................................................................... 29 2.17. PIO ..................................................................................................................................................................... 31 2.17.1. Input Register Block .................................................................................................................................. 31 2.17.2. Output Register Block ............................................................................................................................... 32 2.18. Tri-state Register Block...................................................................................................................................... 33 2.19. DDR Memory Support ....................................................................................................................................... 34 2.19.1. DQS Grouping for DDR Memory ............................................................................................................... 34 2.19.2. DLL Calibrated DQS Delay and Control Block (DQSBUF) ........................................................................... 35 2.20. sysI/O Buffer ...................................................................................................................................................... 37 2.20.1. sysI/O Buffer Banks................................................................................................................................... 37 2.20.2. Typical sysI/O I/O Behavior during Power-up ........................................................................................... 38 2.20.3. Supported sysI/O Standards ..................................................................................................................... 38 2.20.4. On-Chip Programmable Termination ....................................................................................................... 39 2.20.5. Hot Socketing............................................................................................................................................ 39 2.21. SERDES and Physical Coding Sublayer ............................................................................................................... 40 2.21.1. SERDES Block ............................................................................................................................................ 41 2.21.2. PCS ............................................................................................................................................................ 42 2.21.3. SERDES Client Interface Bus ..................................................................................................................... 42 2.22. Flexible Dual SERDES Architecture .................................................................................................................... 42 2.23. IEEE 1149.1-Compliant Boundary Scan Testability ............................................................................................ 43 2.24. Device Configuration ......................................................................................................................................... 43 2.24.1. Enhanced Configuration Options.............................................................................................................. 43 2.24.2. Single Event Upset (SEU) Support............................................................................................................. 44 2.24.3. On-Chip Oscillator ..................................................................................................................................... 44 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02014-1.1