Product Information

LFEC3E-3TN100C

LFEC3E-3TN100C electronic component of Lattice

Datasheet
FPGA LatticeEC Family 3100 Cells 340MHz 130nm Technology 1.2V 100-Pin TQFP

Manufacturer: Lattice
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 22.27 ea
Line Total: USD 22.27

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 1
Multiples : 1
1 : USD 22.27
25 : USD 13.5828
100 : USD 9.8014
500 : USD 7.8386
1000 : USD 7.0027

0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 2
Multiples : 1
2 : USD 22.27
25 : USD 13.5828
100 : USD 9.8014
500 : USD 7.8386
1000 : USD 7.0027

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Product
Series
Number of Logic Elements
Number of I/Os
Operating Supply Voltage
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
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Packaging
Brand
Distributed Ram
Embedded Block Ram - Ebr
Maximum Operating Frequency
Number Of Logic Array Blocks - Labs
Factory Pack Quantity :
Total Memory
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LatticeECP/EC Family Data Sheet DS1000 Version 02.8, September 2012LatticeECP/EC Family Data Sheet Introduction September 2012 Data Sheet LVCMOS 3.3/2.5/1.8/1.5/1.2 Features LVTTL Extensive Density and Package Options SSTL 3/2 Class I, II, SSTL18 Class I 1.5K to 32.8K LUT4s HSTL 18 Class I, II, III, HSTL15 Class I, III 65 to 496 I/Os PCI Density migration supported LVDS, Bus-LVDS, LVPECL, RSDS sysDSP Block (LatticeECP Versions) Dedicated DDR Memory Support High performance multiply and accumulate Implements interface up to DDR400 (200MHz) 4 to 8 blocks sysCLOCK PLLs 4 to 8 36x36 multipliers or Up to four analog PLLs per device 16 to 32 18x18 multipliers or Clock multiply, divide and phase shifting 32 to 64 9x9 multipliers System Level Support Embedded and Distributed Memory IEEE Standard 1149.1 Boundary Scan, plus 18 Kbits to 498 Kbits sysMEM Embedded ispTRACY internal logic analyzer capability Block RAM (EBR) SPI boot flash interface Up to 131 Kbits distributed RAM 1.2V power supply Flexible memory resources: Low Cost FPGA Distributed and block memory Features optimized for mainstream applications Flexible I/O Buffer Low cost TQFP and PQFP packaging Programmable sysI/O buffer supports wide range of interfaces: Table 1-1. LatticeECP/EC Family Selection Guide LFEC6/ LFEC10/ LFEC15/ LFEC20/ LFEC33/ Device LFEC1LFEC3 LFECP6 LFECP10 LFECP15 LFECP20 LFECP33 PFU/PFF Rows 12 16 24 32 40 44 64 PFU/PFF Columns 1624 3240485664 PFUs/PFFs 192 384 768 1280 1920 2464 4096 LUTs (K) 1.5 3.1 6.1 10.2 15.4 19.7 32.8 Distributed RAM (Kbits) 6 12 25 41 61 79 131 EBR SRAM (Kbits) 18 55 92 276 350 424 498 EBR SRAM Blocks 2 6 10 30 38 46 54 1 sysDSP Blocks 45678 1 18x18 Multipliers 16 20 24 28 32 V Voltage (V) 1.2 1.2 1.2 1.2 1.2 1.2 1.2 CC Number of PLLs 2224444 Packages and I/O Combinations: 100-pin TQFP (14 x 14 mm) 67 67 144-pin TQFP (20 x 20 mm) 97 97 97 208-pin PQFP (28 x 28 mm) 112 145 147 147 256-ball fpBGA (17 x 17 mm) 160 195 195 195 484-ball fpBGA (23 x 23 mm) 224 288 352 360 360 672-ball fpBGA (27 x 27 mm) 400 496 1. LatticeECP devices only. 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 Introduction 01.4

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:
LA4
LAT
LATTICE SEMI
Lattice Semiconductor
Lattice Semiconductor Corporation
Vantis

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