ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO SEPTEMBER 2010 REV. 4.2.2 FEATURES GENERAL DESCRIPTION Added feature in devices with top markingA2 The ST16C2552 (2552) is a dual universal YYW and newer: asynchronous receiver and transmitter (UART). The ST16C2552 is an improved version of the PC16552 5 Volt Tolerant Inputs UART. The 2552 provides enhanced UART functions Pin-to-pin and functionally compatible to National with 16 byte FIFOs, a modem control interface, and PC16552 and Exars XR16L2752 and XR16C2852 data rates up to 4 Mbps. Onboard status registers provide the user with error indications and 4 Mbps transmit/receive operation (64 MHz operational status. System interrupts and modem External Clock Frequency) control features may be tailored by external software 2 Independent UART Channels to meet specific user requirements. Indepedendent programmable baud rate generators are privded to Register Set Compatible to 16C550 select transmit and receive clock rates from 50 Bps to 16 byte Transmit FIFO to reduce the bandwidth 4 Mbps. The baud rate generator can be configured requirement of the external CPU for either crystal or external clock input. An internal 16 byte Receive FIFO with error tags to reduce loop-back capability allows onboard diagnostics. The the bandwidth requirement of the external CPU 2552 provides block mode data transfers (DMA) 4 selectable RX FIFO Trigger Levels through FIFO controls. DMA transfer monitoring is provided through the signals TXRDY and RXRDY . Fixed Transmit FIFO interrupt trigger level An Alternate Function Register provides the user with Full Modem Interface (CTS , RTS , DSR , the ability to initialize both UARTs concurrently. The DTR , RI , CD ) 2552 is available in the 44-PLCC package. DMA operation and DMA monitoring via TXRDY APPLICATIONS and RXRDY pins Portable Appliances UART internal register sections A & B may be written to concurrently Telecommunication Network Routers Multi-Function output allows more package Ethernet Network Routers functions with few I/O pins Cellular Data Devices Programmable character lengths (5, 6, 7, 8) with Factory Automation and Process Controls even, odd, or no parity Crystal oscillator or external clock input FIGURE 1. ST16C2552 BLOCK DIAGRAM 3.3V or 5V VCC A2:A0 GND D7:D0 IOR UART Channel A IOW TXA (or TXIRA) 16 Byte TX FIFO CS UART CHSEL Regs TX & RX INTA BRG 16 Byte RX FIFO INTB RXA (or RXIRA) 8-bit Data TXRDYA Bus TXRDYB TXB (or TXIRB) UART Channel B Interface (same as Channel A) MFA RXB (or RXIRB) (OP2A , BAUDOUTA , or RXRDYA ) XTAL1 Crystal Osc/Buffer MFB XTAL2 (OP2B , BAUDOUTB , or CTS A/B, RI A/B, Modem Control Logic RXRDYB ) CD A/B, DSR A/B Reset DTR A/B, RTS A/B 2552BLK Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com ST16C2552 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO REV. 4.2.2 FIGURE 2. PIN OUT ASSIGNMENT D5 7 39 RXA 38 TXA D6 8 D7 9 37 DTRA A0 10 36 RTSA XTAL1 11 35 MFA ST16C2552 GND 12 34 INTA 44-pin PLCC VCC XTAL2 13 33 A1 14 32 TXRDYB A2 15 31 RIB CHSEL 16 30 CDB INTB 17 29 DSRB ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE DEVICE STATUS ST16C2552CJ44 44-Lead PLCC 0C to +70C Active ST16C2552IJ44 44-Lead PLCC -40C to +85C Active 2 CS 18 6 D4 MFB 19 5 D3 20 IOW 4 D2 RESET 21 3 D1 22 GND 2 D0 RTSB 23 1 TXRDYA IOR 24 44 VCC RXB 25 43 RIA TXB 26 42 CDA 27 DTRB 41 DSRA CTSB 28 40 CTSA