XRT6165ID-F MaxLinear

XR-T6165 Codirectional Digital TM ...the analog plus company Data Processor Dec 2010 FEATURES APPLICATIONS Low Power CMOS Technology CCITT G.703 Compliant 64kbps Codirectional Interface All Receiver and Transmitter Inputs and Outputs are TTL Compatible Performs the Digital and Analog Functions for a Transmitter Inhibits Bipolar Violation Insertion for Complete 64kbps Data Adaption Unit (DAU) When Transmission of Alarm Conditions Used With the XR-T6164 Alarm Output Indicates Loss of Received Bipolar Violations Up to 125s Variance of Data Transfer Timing in Both Transmit and Receive Paths Allows Operation in Plesiochronous Networks Both Receiver and Transmitter Perform Byte Insertion or Deletion in Response to Local Clock Slips GENERAL DESCRIPTION The XR-T6165 is a CMOS device which contains the sections. The transmitter transforms 8 bit serial data from digital circuitry necessary to interface both directions of a a 2.048Mbps time-slot into an encoded 64kbps data 64kbps data stream to 2.048Mbps transmit and receive stream. The receiver , which performs the reverse PCM time-slots. The XR-T6165 and the companionoperation, decodes the 64kbps data, extracts a clock XR-T6164 line interface chip together form a CCITT signal, and then outputs the data to a 2.048Mbps G.703 compliant 64kbps codirectional interface. time-slot. The XR-T6165 provides features which allow the repetitions and deletions of both received and The XR-T6165 contains separate transmit and receive transmitted data as clock skews and transients occur. ORDERING INFORMATION Operating Part No. Package Temperature Range XR-T6165CD 24 Lead 300 Mil JEDEC SOIC 0C to +70C XR-T6165ID 24 Lead 300 Mil JEDEC SOIC 40C to +85C Rev. 2.04 3121 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 (510) 668-7010 1XR-T6165 1 (17) 15 PCMIN D 1 8 Bit Input Register (18) 16 TX2MHz CLK Byte 8 Deletion 8 TS1T 8 Bit Latch Time 9 Slot TS2T LOAD Mux Byte 8 1 Insertion (14) 12 TTSEL CLK 8 Bit Output Register LOAD Q Control Circuitry 1 (16) 14 D TX256kHz Octet Violation CLK Counter Insertion Coding T+R Q 10 Logic 1 (15) 13 ALARMIN D CLK 11 Q T-R Note 1 Number in brackets are for SOIC package Figure 1. XR-T6165 Transmit Section Block Diagram Byte Sync 1 Violation (24) Detection Loss 22 ALARM CLK Alarm S+R 1 Data Decoder 2 S-R CLK BLS 3 D Q 1 (23) 21 8 Bit Reg 0 PCMOUT 4 RX2MHz Register CLK Select 1 (20) Logic 18 D Q TS1R 8 Bit Reg 1 Time 1 CLK (21) 19 TS2R Slot REG 0 SEL Mux 1 REG 1 SEL (22) RTSEL 20 Time Slot 128kHz Recovered CLK 5 BLANK Clock Recovery RXCK2MHz 7 Note 1 Number in brackets are for SOIC package Figure 2. XR-T6165 Receiver Section Block Diagram Rev. 2.02 2