XRT7295AEIW-F MaxLinear

XRT7295AE E3 (34.368Mbps) Integrated line Receiver March 2003 APPLICATIONS FEATURES l Interface to E3 Networks l Fully Integrated Receive Interface for E3 Signals l CSU/DSU Equipment l Integrated Equalization (Optional) and Timing l PCM Test Equipment Recovery l Fiber Optic Terminals l Loss-of-Signal and Loss-of-Lock Alarms l Multiplexers l Variable Input Sensitivity Control l 5V Power Supply l Compliant with G703, G.775 and G.824 Specifi- cations GENERAL DESCRIPTION The XRT7295AE E3 Integrated Line Receiver is a fully losses of 0 to 15dB. The receive input has a variable integrates receive interface that terminates a bipolar input sensitivity control, providing three different sen- E3 (34.3684 Mbps) signal transmitted over coaxial sitivity settings. High input sensitivity allows for signifi- Cable. This device can be used with the XRT7296 cant amounts of flat loss or for use with input signals Integrated Line Transmitter (see Figure 10), at the monitor level. Figure 1 shows the block diagram of the device. The device provides the functions of receive equaliza- tion (optional) automatic gain control (AGC), clock The XRT7295AE is manufactured by using linear recovery and data re-timing, loss of signal and loss-of CMOS technology. The XRT7295AE is available in a frequency lock detection. The digital system interface 20-pin plastic SOJ package for surface mounting. A pin is a dual-rail with received positive and negative 1s compatible version is available for DS3 or STS-1 appearing as unipolar digital signals on separate output applications. Please refer to the XRT7295AT data leads. The on-chip equalizer is designed for cable sheet ORDERING INFORMATION Operating Part No. Package Temperature Range XRT7295AEIW 20 J-lead 300 MIL JEDEC SOJ -40C to +85C Rev. 2.0.0 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017XRT7295AE Figure 1. Block Diagram PIN CONFIGURATION Rev. 2.0.0 2