XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT OCTOBER 2003 REV. 1.0.1 FEATURES GENERAL DESCRIPTION Incorporates an improved Timing Recovery circuit The XRT73L03B, 3-Channel, DS3/E3/STS-1 Line In- and is pin and functional compatible to XRT73L03A terface Unit is a low power CMOS version of the XRT73L03A and consists of three independent line Meets E3/DS3/STS-1 Jitter Tolerance Require- transmitters and receivers integrated on a single chip ments designed for DS3, E3 or SONET STS-1 applications. Contains a 4-Wire Microprocessor Serial Interface Each channel of the XRT73L03B can be configured Full Loop-Back Capability to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) Transmit and Receive Power Down Modes or the SONET STS-1 (51.84 Mbps) rates. Each Full Redundancy Support channel can be configured to operate in a mode/data rate that is independent of the other channels. Uses Minimum External components Single +3.3V Power Supply In the transmit direction, each channel encodes input data to either B3ZS (DS3/STS-1) or HDB3 (E3) for- Low power CMOS design mat and converts the data into the appropriate pulse 5V tolerant I/O shapes for transmission over coaxial cable via a 1:1 -40C to +85C Operating Temperature Range transformer. Available in a 120 pin LQFP package In the receive direction, the XRT73L03B performs equalization on incoming signals, performs Clock Re- APPLICATIONS covery, decodes data from either B3ZS or HDB3 for- Digital Cross Connect Systems mat, converts the receive data into TTL/CMOS for- CSU/DSU Equipment mat, checks for LOS or LOL conditions and detects Routers and declares the occurrence of Line Code Violations. Fiber Optic Terminals Multiplexers ATM Switches FIGURE 1. XRT73L03B BLOCK DIAGRAM E3 (n) STS-1/DS3 (n) Host/(HW) RLOL (n) RxOFF RxClkINV EXClk (n) RTIP (n) AGC/ Clock Slicer Invert RxClk (n) RRing (n) Equalizer Recovery Peak REQEN (n) Data RPOS (n) HDB3/ Detector Recovery B3ZS RNEG (n) Decoder LOS Detector LCV (n) LOSTHR (n) ENDECDIS SDI RLOS (n) SDO Serial Processor LLB (n) SClk Loop MUX Interface CS RLB (n) REGR TAOS (n) TTIP (n) TPData (n) HDB3/ Transmit Pulse B3ZS Logic TNData (n) Shaping Encoder Duty Cycle Adjust TxClk (n) TRing (n) TxLEV (n) MTIP (n) Tx Device Control TxOFF (n) Monitor MRing (n) Channel 0 - (n) = 0 DMO (n) Channel 1 - (n) = 1 Channel 2 - (n) = 2 Notes: 1. (n) = 0, 1, or 2 for respective Channels 2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode. Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 TYPICAL APPLICATIONS FIGURE 2. MULTICHANNEL ATM APPLICATION RPOS RPOS RPOS RRPOS RTIP RNEG RNEG RNEG RRNEG RRing RxClk RxClk RxLineClk RRClk ATM Switch/ XRT74L73 XRT71D03 XRT73L03B SAR MClk TPOS TPOS TTIP TNEG TNEG TRing TxClk TxLineClk 3 Channel E3/DS3 ATM 3 Channel E3/DS3 J/A 3 Channel E3/DS3 LIU UNI FIGURE 3. MULTISERVICE - FRAME RELAY APPLICATION RPOS RRPOS RPOS RPOS RTIP RNEG RRNEG RNEG RNEG RRing RxLineClk RRClk RxClk RxClk Frame Relay XRT71D03 XRT73L03B XRT72L56 MClk TPOS TPOS TTIP TNEG TNEG TRing TxLineClk TxClk 6 Channel E3/DS3 Framer 2 x 3 Channel E3/DS3 J/A 2 x 3 Channel E3/DS3 LIU TRANSMIT INTERFACE CHARACTERISTICS: RECEIVE INTERFACE CHARACTERISTICS: Accepts either Single-Rail or Dual-Rail data from Integrated Adaptive Receive Equalization (optional) Terminal Equipment and generates a bipolar signal and Timing Recovery from the line Declares and Clears the LOS defect per ITU-T Integrated Pulse Shaping Circuit G.775 requirements (E3 and DS3 applications) Built-in B3ZS/HDB3 Encoder (which can be dis- Meets Jitter Tolerance Requirements as specified in abled) ITU-T G.823 1993 (E3 Applications) Contains Transmit Clock Duty Cycle Correction Cir- Meets Jitter Tolerance Requirements as specified in cuit on-chip Bellcore GR-499-CORE (DS3 Applications) Generates pulses that comply with the ITU-T G.703 Declares Loss of Signal (LOS) and Loss of Lock pulse template (E3 applications) (LOL) Alarms Generates pulses that comply with the DSX-3 pulse Built-in B3ZS/HDB3 Decoder (which can be dis- template as specified in Bellcore GR-499-CORE abled) and ANSI T1.102 1993 Recovered Data can be muted while the LOS Con- Generates pulses that comply with the STSX-1 dition is declared pulse template as specified in Bellcore GR-253- Outputs either Single-Rail or Dual-Rail data to the CORE Terminal Equipment Transmitter can be turned off in order to support Receiver can be powered down in order to con- redundancy designs serve power in redundancy designs 2