XRT75L03 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR JULY 2003 REV. 1.0.4 TRANSMITTER: GENERAL DESCRIPTION Compliant with Bellcore GR-499, GR-253 and ANSI The XRT75L03 is a three-channel fully integrated T1.102 Specification for transmit pulse Line Interface Unit (LIU) with Jitter Attenuator for E3/ DS3/STS-1 applications. It incorporates 3 Tri-state Transmit output capability for redundancy independent Receivers, Transmitters and Jitter applications Attenuators in a single 128 pin LQFP package. Each Transmitter can be turned on or off Each channel of the XRT75L03 can be independently Transmitters provide Current Output Drive configured to operate in the data rate, E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz). JITTER ATTENUATOR: Each transmitter can be turned off and tri-stated for On chip advanced crystal-less Jitter Attenuator for redundancy support or for conserving power. each channel The XRT75L03s differential receiver provides high Jitter Attenuator can be selected in Receive or noise interference margin and is able to receive the Transmit paths data over 1000 feet of cable or with up to 12 dB of cable attenuation. Meets ETSI TBR 24 Jitter Transfer Requirements The XRT75L03 incorporates an advanced crystal- Compliant with jitter transfer template outlined in less jitter attenuator per channel that can be selected ITU G.751, G.752, G.755 and GR-499-CORE,1995 either in the transmit or receive path. The jitter standards attenuator performance meets the ETSI TBR-24 and 16 or 32 bits selectable FIFO size Bellcore GR-499 specifications. The XRT75L03 provides both Serial Microprocessor Jitter Attenuator can be disabled Interface as well as Hardware mode for programming CONTROL AND DIAGNOSTICS: and control. 5 wire Serial Microprocessor Interface for control The XRT75L03 supports local, remote and digital and configuration loop-backs. The device also has a built-in Pseudo Supports optional internal Transmit driver Random Binary Sequence (PRBS) generator and monitoring detector with the ability to insert and detect single bit error for diagnostic purposes. Hardware Mode for control and configuration FEATURES Each channel supports Local, Remote and Digital Loop-backs RECEIVER: Single 3.3 V 5% power supply On chip Clock and Data Recovery circuit for high input jitter tolerance 5 V Tolerant digital inputs Meets E3/DS3/STS-1 Jitter Tolerance Requirement Available in 128 pin LQFP Package Detects and Clears LOS as per G.775 - 40C to 85C Industrial Temperature Range Receiver Monitor mode handles up to 20 dB flat APPLICATIONS loss with 6 dB cable attenuation E3/DS3 Access Equipment On chip B3ZS/HDB3 encoder and decoder that can be either enabled or disabled DSLAMs On-chip clock synthesizer provides the appropriate Digital Cross Connect Systems rate clock from a single 12.288 MHz Clock CSU/DSU Equipment Provides low jitter output clock Routers Fiber Optic Terminals Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT75L03 REV. 1.0.4 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L03 SDI CLKOUT XRT75L03 SDO XRT75L03 E3Clk,DS3Clk, Serial INT STS-1Clk Processor SClk Interface RLOL (n) CS RxON RESET RxClkINV Clock HOST/HW Invert RxClk (n) Peak Detector Synthesizer STS-1/DS3 (n) E3 (n) HDB3/ RPOS (n) REQEN (n) Clock & Data Jitter Slicer B3ZS AGC/ MUX RNEG (n)/ RTIP (n) Recovery Attenuator Equalizer Decoder LCV (n) RRing (n) LOS SR/DR Remote Detector Local LoopBack RLB (n) LLB (n) LoopBack RLOS (n) LOSTHR JATx/Rx TTIP (n) TPData (n) HDB3/ Line Tx Jitter Timing MUX B3ZS Driver Pulse TNData (n) Attenuator TRing (n) Control Encoder Shaping TxClk (n) TAOS (n) MTIP (n) Device MRing (n) Tx TxLEV (n) Monitor Control TxON (n) Channel 0 DMO (n) Channel 1 Channel 2 Notes: 1. (n) = 0, 1 or 2 for respective Channels 2. Serial Processor Interface input pins are shared by the three Channels inHos Mode and redefined in theHardwar Mode. TRANSMIT INTERFACE CHARACTERISTICS Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the line Integrated Pulse Shaping Circuit Built-in B3ZS/HDB3 Encoder (which can be disabled) Accepts Transmit Clock with duty cycle of 30%-70% Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and ANSI T1.102 1993 Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE Transmitter can be turned off in order to support redundancy designs RECEIVE INTERFACE CHARACTERISTICS Integrated Adaptive Receive Equalization (optional) for optimal Clock and Data Recovery Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications Meets Jitter Tolerance Requirements, as specified in ITU-T G.823 1993 for E3 Applications Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms Built-in B3ZS/HDB3 Decoder (which can be disabled) Recovered Data can be muted while the LOS Condition is declared Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment 2