XRT83SL28IV-F MaxLinear

xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT APRIL 2005 REV. 1.0.0 Additional features include TAOS for transmit and GENERAL DESCRIPTION receive, RLOS, LCV, AIS, DMO, and diagnostic The XRT83SL28 is a fully integrated 8-channel E1 loopback modes. short-haul LIU which optimizes system cost and APPLICATIONS performance by offering key design features. The XRT83SL28 operates from a single 3.3V power ISDN Primary Rate Interface supply. The LIU features are programmed through a CSU/DSU E1 Interface standard serial microprocessor interface or hardware control. EXARs LIU has patented high impedance E1 LAN/WAN Routers circuits that allow the transmitter outputs and receiver Public Switching Systems and PBX Interfaces inputs to be high impedance when experiencing a E1 Multiplexer and Channel Banks power failure or when the LIU is powered off. Key design features within the LIU optimize 1:1 or 1+1 Integrated Multi-Service Access Platforms (IMAPs) redundancy and non-intrusive monitoring applications Integrated Access Devices (IADs) to ensure reliability without using relays. Inverse Multiplexing for ATM (IMA) Wireless Base Stations FIGURE 1. HOST MODE BLOCK DIAGRAM OF THE XRT83SL28 1 of 8 Channels Driver DMO Monitor TTIP TCLK HDB3 Timing Tx Pulse Line TPOS Encoder Control Shaper Driver TNEG TRING Remote Digital Analog Loopback Loopback Loopback Jitter Attenuator (Rx or Tx) RTIP Peak RCLK HDB3 Clock & Data Rx RPOS Detector Decoder Recovery Equalizer RNEG/LCV & Slicer RRING RLOS AIS & LOS Detector Test ICT Clock Distribution Serial Microprocessor TxOE Interface Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com INT CS SCLK SDI SDO HW/Host Reset MCLKXRT83SL28 xr 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 FIGURE 2. HARDWARE MODE BLOCK DIAGRAM OF THE XRT83SL28 1 of 8 Channels Driver DMO Monitor TTIP TCLK HDB3 Timing Tx Pulse Line TPOS Encoder Control Shaper Driver TNEG/CODE TRING Remote Digital Analog Loopback Loopback Loopback Jitter Attenuator (Rx or Tx) Peak RTIP RCLK HDB3 Clock & Data Rx RPOS Detector Decoder Recovery Equalizer RNEG/LCV & Slicer RRING RLOS AIS & LOS Detector Test ICT Clock Distribution TxOE Hardware Configuration 2 SR/DR TERSEL 1:0 TCLKinv RCLKinv LBM 1:0 JASEL 1:0 FIFOS CHLB 3:0 HW/Host Reset MCLK